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| 1 features ? avr - high performance and low power risc architecture ? 118 powerful instructions - most single clock cycle execution ? 8k bytes of in-system reprogrammable flash C spi serial interface for program downloading C endurance: 1,000 write/erase cycles ? 512 bytes eeprom C endurance: 100,000 write/erase cycles ? 512 bytes internal sram ? 32 x 8 general purpose working registers ? 32 programmable i/o lines ? programmable serial uart ? spi serial interface ? v cc : 2.7 - 6.0v ? fully static operation C 0 - 8 mhz 4.0 - 6.0v, C 0 - 4 mhz 2.7 - 4.0v ? up to 8 mips throughput at 8 mhz ? one 8-bit timer/counter with separate prescaler ? one 16-bit timer/counter with separate prescaler and compare and capture modes ? dual pwm ? external and internal interrupt sources ? programmable watchdog timer with on-chip oscillator ? on-chip analog comparator ? low power idle and power down modes ? programming lock for software security description the at90s8515 is a low-power cmos 8-bit microcontroller based on the avr ? enhanced risc architecture. by executing powerful instructions in a single clock cycle, the at90s8515 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. the avr core combines a rich instruction set with 32 general purpose working regis- ters. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. rev. 0841dC06/98 8-bit microcontroller with 8k bytes in-system programmable flash at90s8515 preliminary pin configurations (continued)
at90s8515 2 block diagram figure 1. the at90s8515 block diagram the at90s8515 provides the following features: 8k bytes of in-system programmable flash, 512 bytes eeprom, 512 bytes sram, 32 general purpose i/o lines, 32 general purpose working registers, flexible timer/counters with compare modes, internal and external interrupts, a pro- grammable serial uart, programmable watchdog timer with internal oscillator, an spi serial port and two software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port and interrupt system to continue functioning. the power down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. the device is manufactured using atmels high density non-volatile memory technology. the on-chip in-system programmable flash allows the program memory to be reprogrammed in-system through an spi serial interface or by a conventional nonvolatile memory programmer. by combining an enhanced risc 8-bit cpu with in-system programmable flash on a monolithic chip, the atmel at90s8515 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embed- ded control applications. the at90s8515 avr is supported with a full suite of pro- gram and system development tools including: c compil- ers, macro assemblers, program debugger/simulators, in- circuit emulators, and evaluation kits. at90s8515 3 pin descriptions v cc supply voltage gnd ground port a (pa7..pa0) port a is an 8-bit bidirectional i/o port. port pins can pro- vide internal pull-up resistors (selected for each bit). the port a output buffers can sink 20ma and can drive led dis- plays directly. when pins pa0 to pa7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. port a serves as multiplexed address/data input/output when using external sram. port b (pb7..pb0) port b is an 8-bit bidirectional i/o pins with internal pull-up resistors. the port b output buffers can sink 20 ma. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. port b also serves the functions of various special features of the at90s8515 as listed on page 46. port c (pc7..pc0) port c is an 8-bit bidirectional i/o port with internal pull-up resistors. the port c output buffers can sink 20 ma. as inputs, port c pins that are externally pulled low will source current if the pull-up resistors are activated. port c also serves as address output when using external sram. port d (pd7..pd0) port d is an 8-bit bidirectional i/o port with internal pull-up resistors. the port d output buffers can sink 20 ma. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. port d also serves the functions of various special features of the at90s8515 as listed on page 52. reset reset input. a low on this pin for two machine cycles while the oscillator is running resets the device. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier icp icp is the input pin for the timer/counter1 input capture function. oc1b oc1b is the output pin for the timer/counter1 output compareb function ale ale is the address latch enable used when the external memory is enabled. the ale strobe is used to latch the low-order address (8 bits) into an address latch during the first access cycle, and the ad0-7 pins are used for data during the second access cycle. crystal oscillator xtal1 and xtal2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 2. either a quartz crystal or a ceramic resonator may be used. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven as shown in figure 3. figure 2. oscillator connections figure 3. external clock drive configuration at90s8515 4 at90s8515 architectural overview the fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. this means that during one single clock cycle, one alu (arithmetic logic unit) operation is executed. two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. six of the 32 registers can be used as three 16-bits indirect address register pointers for data space addressing - enabling efficient address calculations. one of the three address pointers is also used as the address pointer for the constant table look up function. these added function reg- isters are the 16-bits x-register, y-register and z-register. figure 4. the at90s8515 avr enhanced risc architecture the alu supports arithmetic and logic functions between registers or between a constant and a register. single reg- ister operations are also executed in the alu. figure 4 shows the at90s8515 avr enhanced risc microcontrol- ler architecture. in addition to the register operation, the conventional mem- ory addressing modes can be used on the register file as well. this is enabled by the fact that the register file is assigned the 32 lowermost data space addresses ($00 - $1f), allowing them to be accessed as though they were ordinary memory locations. the i/o memory space contains 64 addresses for cpu peripheral functions as control registers, timer/counters, a/d-converters, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, $20 - $5f. the avr uses a harvard architecture concept - with sepa- rate memories and buses for program and data. the pro- gram memory is executed with a two stage pipeline. while one instruction is being executed, the next instruction is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system programmable flash memory. with the relative jump and call instructions, the whole 4k address space is directly accessed. most avr instructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and conse- quently the stack size is only limited by the total sram size and the usage of the sram. all user programs must initial- at90s8515 5 ize the sp in the reset routine (before subroutines or inter- rupts are executed). the 16-bit stack pointer sp is read/write accessible in the i/o space. the 512 bytes data sram can be easily accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the status register. all the different interrupts have a sepa- rate interrupt vector in the interrupt vector table at the beginning of the program memory. the different interrupts have priority in accordance with their interrupt vector posi- tion. the lower the interrupt vector address the higher the priority. figure 5. memory maps the general purpose register file figure 6 shows the structure of the 32 general purpose working registers in the cpu. figure 6. avr cpu general purpose working registers all the register operating instructions in the instruction set have direct and single cycle access to all registers. the only exception is the five constant arithmetic and logic instructions sbci, subi, cpi, andi and ori between a constant and a register and the ldi instruction for load immediate constant data. these instructions apply to the second half of the registers in the register file - r16..r31. the general sbc, sub, cp, and and or and all other operations between two registers or on a single register apply to the entire register file. as shown in figure 6, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being phys- ically implemented as sram locations, this memory orga- nization provides great flexibility in access of the registers, as the x,y and z registers can be set to index any register in the file. 70addr. r0 $00 r1 $01 r2 $02 r13 $0d general r14 $0e purpose r15 $0f working r16 $10 registers r17 $11 r26 $1a x-register low byte r27 $1b x-register high byte r28 $1c y-register low byte r29 $1d y-register high byte r30 $1e z-register low byte r31 $1f z-register high byte at90s8515 6 the x-register, y-register and z-register the registers r26..r31 have some added functions to their general purpose usage. these registers are address point- ers for indirect addressing of the data space. the three indirect address registers x, y and z are defined as: figure 7. the x, y and z registers in the different addressing modes these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions). the alu - arithmetic logic unit the high-performance avr alu operates in direct connec- tion with all the 32 general purpose working registers. within a single clock cycle, alu operations between regis- ters in the register file are executed. the alu operations are divided into three main categories - arithmetic, logical and bit-functions. the in-system programmable flash program memory the at90s8515 contains 8k bytes on-chip in-system pro- grammable flash memory for program storage. since all instructions are 16-or 32-bit words, the flash is organized as 4k x 16. the flash memory has an endurance of at least 1000 write/erase cycles. the at90s8515 program counter (pc) is 12 bits wide, thus addressing the 4096 pro- gram memory addresses. see page 62 for a detailed description on flash data down- loading. constant tables must be allocated within the address 0-4k (see the lpm - load program memory instruction descrip- tion). see page 8 for the different program memory addressing modes. 15 0 x - register 7 0 7 0 r27 ($1b) r26 ($1a) 15 0 y - register 7 0 7 0 r29 ($1d) r28 ($1c) 15 0 z - register 7 0 7 0 r31 ($1f) r30 ($1e) at90s8515 7 the sram data memory - internal and external the following figure shows how the at90s8515 sram memory is organized: figure 8. sram organization the lower 608 data memory locations address the regis- ter file, the i/o memory and the internal data sram. the first 96 locations address the register file + i/o memory, and the next 512 locations address the internal data sram. an optional external data sram can be placed in the same sram memory space. this sram will occupy the location following the internal sram and up to as much as 64k - 1, depending on sram size. when the addresses accessing the data memory space exceeds the internal data sram locations, the external data sram is accessed using the same instructions as for the internal data sram access. when the internal data space is accessed, the read and write strobe pins (rd and wr ) are inactive during the whole access cycle. external sram operation is enabled by setting the sre bit in the mcucr register. see page 21 for details. accessing external sram takes one additional clock cycle per byte compared to access of the internal sram. this means that the commands ld, st, lds, sts, push and pop take one additional clock cycle. if the stack is placed in external sram, interrupts, subroutine calls and returns take two clock cycles extra because the two-byte program counter is pushed and popped. when external sram inter- face is used with wait state, two additional clock cycles is used per byte. this has the following effect: data transfer instructions take two extra clock cycles, whereas interrupt, subroutine calls and returns will need four clock cycles more than specified in the instruction set manual. the five different addressing modes for the data memory cover: direct, indirect with displacement, indirect, indirect with pre-decrement and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. register file data address space r0 $0000 r1 $0001 r2 $0002 ?? r29 $001d r30 $001e r31 $001f i/o registers $00 $0020 $01 $0021 $02 $0022 $3d $005d $3e $005e $3f $005f internal sram $0060 $0061 ? $025e $025f external sram $0260 $0261 $fffe $ffff at90s8515 8 the direct addressing reaches the entire data space. the indirect with displacement mode features a 63 address locations reach from the base address given by the y or z-register. when using register indirect addressing modes with auto- matic pre-decrement and post-increment, the address reg- isters x, y and z are decremented and incremented. the 32 general purpose working registers, 64 i/o registers, the 512 bytes of internal data sram, and the 64k bytes of optional external data sram in the at90s8515 are all accessible through all these addressing modes. see the next section for a detailed description of the differ- ent addressing modes. the program and data addressing modes the at90s8515 avr enhanced risc microcontroller sup- ports powerful and efficient addressing modes for access to the program memory (flash) and data memory (sram, register file and i/o memory). this section describes the different addressing modes supported by the avr architec- ture. in the figures, op means the operation code part of the instruction word. to simplify, not all figures show the exact location of the addressing bits. register direct, single register rd figure 9. direct single register addressing the operand is contained in register d (rd). register direct, two registers rd and rr figure 10. direct register addressing, two registers operands are contained in register r (rr) and d (rd). the result is stored in register d (rd). i/o direct figure 11. i/o direct addressing operand address is contained in 6 bits of the instruction word. n is the destination or source register address. data direct figure 12. direct data addressing a 16-bit data address is contained in the 16 lsbs of a two- word instruction. rd/rr specify the destination or source register. data indirect with displacement figure 13. data indirect with displacement operand address is the result of the y or z-register con- tents added to the address contained in 6 bits of the instruction word. at90s8515 9 data indirect figure 14. data indirect addressing operand address is the contents of the x, y or the z-regis- ter. data indirect with pre-decrement figure 15. data indirect addressing with pre-decrement the x, y or the z-register is decremented before the opera- tion. operand address is the decremented contents of the x, y or the z-register. data indirect with post-increment figure 16. data indirect addressing with post-increment the x, y or the z-register is incremented after the opera- tion. operand address is the content of the x, y or the z- register prior to incrementing. constant addressing using the lpm instruction figure 17. code memory constant addressing constant byte address is specified by the z-register con- tents. the 15 msbs select word address (0 - 4k) and lsb, select low byte if cleared (lsb = 0) or high byte if set (lsb = 1). indirect program addressing, ijmp and icall figure 18. indirect program memory addressing program execution continues at address contained by the z-register (i.e. the pc is loaded with the contents of the z- register). relative program addressing, rjmp and rcall figure 19. relative program memory addressing program execution continues at address pc + k + 1. the relative address k is -2048 to 2047. at90s8515 10 the eeprom data memory the at90s8515 contains 512 bytes of data eeprom memory. it is organized as a separate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described on page 32 specifying the eeprom address registers, the eeprom data register, and the eeprom control register. for the spi data downloading, see page 62 for a detailed description. memory access times and instruction execution timing this section describes the general access timing concepts for instruction execution and internal memory access. the avr cpu is driven by the system clock ?, directly generated from the external clock crystal for the chip. no internal clock division is used. figure 20 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corresponding unique results for functions per cost, func- tions per clocks, and functions per power-unit. figure 20. the parallel instruction fetches and instruction executions figure 21 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two reg- ister operands is executed, and the result is stored back to the destination register. figure 21. single cycle alu operation the internal data sram access is performed in two system clock cycles as described in figure 22. system clock ? 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 system clock ? total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 at90s8515 11 figure 22. on-chip data sram access cycles the external data sram access is performed in two system clock cycles as described in figure 22. figure 23. external data sram memory cycles without wait state the external data sram memory access cycle with the wait state bit enabled (wait state active) is shown in figure 24 . figure 24. external data sram memory cycles with wait state system clock ? wr rd data data address address t1 t2 t3 t4 prev. address read write system clock ? ale wr rd data / address [7..0] data / address [7..0] address [15..8] address address address t1 t2 t3 prev. address prev. address prev. address data data write read address address system clock ? ale wr rd data / address [7..0] data / address [7..0] address [15..8] address address address t1 t2 t3 t4 prev. address prev. address prev. address data data write read addr. addr. at90s8515 12 i/o memory the i/o space definition of the at90s8515 is shown in the following table: table 1. at90s8515 i/o space address hex name function $3f ($5f) sreg status register $3e ($5e) sph stack pointer high $3d ($5d) spl stack pointer low $3b ($5b) gimsk general interrupt mask register $3a ($5a) gifr general interrupt flag register $39 ($59) timsk timer/counter interrupt mask register $38 ($58) tifr timer/counter interrupt flag register $35 ($55) mcucr mcu general control register $33 ($53) tccr0 timer/counter0 control register $32 ($52) tcnt0 timer/counter0 (8-bit) $2f ($4f) tccr1a timer/counter1 control register a $2e ($4e) tccr1b timer/counter1 control register b $2d ($4d) tcnt1h timer/counter1 high byte $2c ($4c) tcnt1l timer/counter1 low byte $2b ($4b) ocr1ah timer/counter1 output compare register a high byte $2a ($4a) ocr1al timer/counter1 output compare register a low byte $29 ($49) ocr1bh timer/counter1 output compare register b high byte $28 ($48) ocr1bl timer/counter1 output compare register b low byte $25 ($45) icr1h t/c 1 input capture register high byte $24 ($44) icr1l t/c 1 input capture register low byte $21 ($41) wdtcr watchdog timer control register $1f ($3e) eearh eeprom address register high byte $1e ($3e) eearl eeprom address register low byte $1d ($3d) eedr eeprom data register $1c ($3c) eecr eeprom control register $1b ($3b) porta data register, port a $1a ($3a) ddra data direction register, port a $19 ($39) pina input pins, port a $18 ($38) portb data register, port b $17 ($37) ddrb data direction register, port b $16 ($36) pinb input pins, port b $15 ($35) portc data register, port c $14 ($34) ddrc data direction register, port c $13 ($33) pinc input pins, port c at90s8515 13 note: reserved and unused locations are not shown in the table all the different at90s8515 i/os and peripherals are placed in the i/o space. the different i/o locations are accessed by the in and out instructions transferring data between the 32 general purpose working registers and the i/o space. i/o registers within the address range $00 - $1f are directly bit-accessible using the sbi and cbi instruc- tions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. refer to the instruction set chapter for more details. when using the i/o specific commands, in, out,sbis and sbic, the i/o addresses $00 - $3f must be used. when addressing i/o registers as sram, $20 must be added to this address. all i/o register addresses throughout this doc- ument are shown with the sram address in parentheses. the different i/o and peripherals control registers are explained in the following chapters. the status register - sreg the avr status register - sreg - at i/o space location $3f ($5f) is defined as: ? bit 7 - i: global interrupt enable the global interrupt enable bit must be set (one) for the interrupts to be enabled. the individual interrupt enable control is then performed in the interrupt mask registers - gimsk and timsk. if the global interrupt enable register is cleared (zero), none of the interrupts are enabled indepen- dent of the gimsk and timsk values. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. ? bit 6 - t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t bit as source and destination for the oper- ated bit. a bit from a register in the register file can be cop- ied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 - h: half carry flag the half carry flag h indicates a half carry in some arith- metic operations. see the instruction set description for detailed information. ? bit 4 - s: sign bit, s = n ? v the s-bit is always an exclusive or between the negative flag n and the twos complement overflow flag v. see the instruction set description for detailed information. ? bit 3 - v: twos complement overflow flag the twos complement overflow flag v supports twos com- plement arithmetics. see the instruction set description for detailed information. ? bit 2 - n: negative flag the negative flag n indicates a negative result after the dif- ferent arithmetic and logic operations. see the instruction set description for detailed information. ? bit 1 - z: zero flag the zero flag z indicates a zero result after the different arithmetic and logic operations. see the instruction set description for detailed information. $12 ($32) portd data register, port d $11 ($31) ddrd data direction register, port d $10 ($30) pind input pins, port d $0f ($2f) spdr spi i/o data register $0e ($2e) spsr spi status register $0d ($2d) spcr spi control register $0c ($2c) udr uart i/o data register $0b ($2b) usr uart status register $0a ($2a) ucr uart control register $09 ($29) ubrr uart baud rate register $08 ($28) acsr analog comparator control and status register table 1. at90s8515 i/o space (continued) address hex name function bit 76543210 $3f ($5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 at90s8515 14 ? bit 0 - c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the instruction set description for detailed information. the stack pointer - sp the general avr 16-bit stack pointer is effectively built up of two 8-bit registers in the i/o space locations $3e ($5e) and $3d ($5d). as the at90s8515 supports up to 64 kb external sram, all 16-bits are used. the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or inter- rupts are enabled. the stack pointer is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two when data is pushed onto the stack with subroutine call and interrupt. the stack pointer is incremented by one when data is popped from the stack with the pop instruction, and it is incremented by two when data is popped from the stack with return from subroutine ret or return from interrupt iret. reset and interrupt handling the at90s8515 provides 12 different interrupt sources. these interrupts and the separate reset vector, each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be set (one) together with the i-bit in the status regis- ter in order to enable the interrupt. the lowest addresses in the program memory space are automatically defined as the reset and interrupt vectors. the complete list of vectors is shown in table 2. the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and next is int0 - the external interrupt request 0 etc. bit 151413121110 9 8 $3e ($5e) sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph $3d ($5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00000000 at90s8515 15 the most typical and general program setup for the reset and interrupt vector addresses are: address labels code comments $000 rjmp reset ; reset handler $001 rjmp ext_int0 ; irq0 handler $002 rjmp ext_int1 ; irq1 handler $003 rjmp tim1_capt ; timer1 capture handler $004 rjmp tim1_compa ; timer1 comparea handler $005 rjmp tim1_compb ; timer1 compareb handler $006 rjmp tim1_ovf ; timer1 overflow handler $007 rjmp tim0_ovf ; timer0 overflow handler $008 rjmp spi_stc ; spi transfer complete handler $009 rjmp uart_rxc ; uart rx complete handler $00a rjmp uart_dre ; udr empty handler $00b rjmp uart_txc ; uart tx complete handler $00c rjmp ana_comp ; analog comparator handler ; $00d main: at90s8515 16 figure 25. reset logic power-on reset a power-on reset (por) circuit ensures that the device is not started until v cc has reached a safe level. as shown in figure 25, an internal timer clocked from the watchdog timer oscillator prevents the mcu from starting until after a certain period after v cc has reached the power-on thresh- old voltage - v pot , regardless of the v cc rise time (see fig- ure 26 and figure 27). the total reset period is the power- on reset period - t por + the delay time-out period - t tout . the fstrt fuse bit in the flash can be programmed to give a shorter start-up time if a ceramic resonator or any other fast-start oscillator is used to clock the mcu. if the build-in start-up delay is sufficient, reset can be connected to v cc directly or via an external pull-up resistor. by holding the pin low for a period after v cc has been applied, the power-on reset period can be extended. refer to figure 28 for a timing example on this. figure 26. mcu start-up, reset tied to v cc . rapidly rising v cc table 3. reset characteristics (v cc = 5.0v) symbol parameter min typ max units v pot power-on reset threshold voltage 1.8 2 2.2 v v rst r eset pin threshold voltage v cc /2 v t por power-on reset period 2 3 4 ms t tout reset delay time-out period fstrt unprogrammed 11 16 21 ms t tout reset delay time-out period fstrt programmed 1.0 1.1 1.2 ms at90s8515 17 figure 27. mcu start-up, reset tied to v cc or unconnected. slowly rising v cc figure 28. mcu start-up, reset controlled externally external reset an external reset is generated by a low level on the reset pin. the reset pin must be held low for at least two crys- tal clock cycles. when the applied signal reaches the reset threshold voltage - v rst on its positive edge, the delay timer starts the mcu after the time-out period t tout has expired. at90s8515 18 figure 29. external reset during operation watchdog reset when the watchdog times out, it will generate a short reset pulse of 1 xtal cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 30 for details on operation of the watchdog. figure 30. watchdog reset during operation interrupt handling the at90s8515 has two 8-bit interrupt mask control regis- ters; gimsk - general interrupt mask register and timsk - timer/counter interrupt mask register. when an interrupt occurs, the global interrupt enable i-bit is cleared (zero) and all interrupts are disabled. the user software must set (one) the i-bit to enable interrupts. when the program counter is vectored to the actual inter- rupt vector in order to execute the interrupt handling rou- tine, hardware clears the corresponding flag that generated the interrupt. some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. the general interrupt mask register - gimsk ? bit 7 - int1: external interrupt request 1 enable when the int1 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is activated. the interrupt sense control1 bits 1/0 (isc11 and isc10) in the mcu general control register (mcucr) defines whether the external interrupt is activated on rising or falling edge of the int1 pin or level sensed. activity on the pin will cause an interrupt request even if int1 is con- figured as an output. the corresponding interrupt of exter- nal interrupt request 1 is executed from program memory address $002. see also external interrupts. bit 7 6 5 4 3 2 1 0 $3b ($5b) int1 int0 - - - - - - gimsk read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 at90s8515 19 ? bit 6 - int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is activated. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the mcu general control register (mcucr) defines whether the external interrupt is activated on rising or falling edge of the int0 pin or level sensed. activity on the pin will cause an interrupt request even if int0 is con- figured as an output. the corresponding interrupt of exter- nal interrupt request 0 is executed from program memory address $001. see also external interrupts. ? bits 5..0 - res: reserved bits these bits are reserved bits in the at90s8515 and always read as zero. the general interrupt flag register - gifr ? bit 7 - intf1: external interrupt flag1 when an event on the int1 pin triggers an interrupt request, intf1 becomes set (one). if the i-bit in sreg and the int1 bit in gimsk are set (one), the mcu will jump to the interrupt vector at address $002. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. ? bit 6 - intf0: external interrupt flag0 when an event on the int0 pin triggers an interrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in gimsk are set (one), the mcu will jump to the interrupt vector at address $001. the flag is cleared when the interrupt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. ? bits 5..0 - res: reserved bits these bits are reserved bits in the at90s8515 and always read as zero. the timer/counter interrupt mask register - timsk ? bit 7 - toie1: timer/counter1 overflow interrupt enable when the toie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt (at vector $006) is executed if an overflow in timer/counter1 occurs. the overflow flag (timer/counter1) is set (one) in the timer/counter interrupt flag register - tifr. when timer/counter1 is in pwm mode, the timer overflow flag is set when the counter changes counting direction at $0000. ? bit 6 - oce1a:timer/counter1 output comparea match interrupt enable when the ocie1a bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 comparea match interrupt is enabled. the corresponding interrupt (at vector $004) is executed if a comparea match in timer/counter1 occurs. the comparea flag in timer/counter1 is set (one) in the timer/counter interrupt flag register - tifr. ? bit 5 - ocie1b:timer/counter1 output compareb match interrupt enable when the ocie1b bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 compareb match interrupt is enabled. the corresponding interrupt (at vector $005) is executed if a compareb match in timer/counter1 occurs. the compareb flag in timer/counter1 is set (one) in the timer/counter interrupt flag register - tifr. ? bit 4 - res: reserved bit this bit is a reserved bit in the at90s8515 and always reads zero. ? bit 3 - ticie1: timer/counter1 input capture interrupt enable when the ticie1 bit is set (one) and the i-bit in the status register is set (one), the timer/counter1 input capture event interrupt is enabled. the corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, icp. the input capture flag in timer/counter1 is set (one) in the timer/counter interrupt flag register - tifr. ? bit 2 - res: reserved bit this bit is a reserved bit in the at90s8515 and always reads zero. ? bit 1 - toie0: timer/counter0 overflow interrupt enable when the toie0 bit is set (one) and the i-bit in the status register is set (one), the timer/counter0 overflow interrupt is enabled. the corresponding interrupt (at vector $008) is executed if an overflow in timer/counter0 occurs. the bit 7 6 5 4 3 2 1 0 $3a ($5a) intf1 intf0 - - - - - - gifr read/write r/w r/w r r r r r r initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 $39 ($59) toie1 ocie1a ocie1b - ticie1 - toie0 - timsk read/write r/w r/w r/w r r/w r r/w r initial value 0 0 0 0 0 0 0 0 at90s8515 20 overflow flag (timer0) is set (one) in the timer/counter interrupt flag register - tifr. ? bit 0 - res: reserved bit this bit is a reserved bit in the at90s8515 and always reads zero. the timer/counter interrupt flag register - tifr ? bit 7 - tov1: timer/counter1 overflow flag the tov1 is set (one) when an overflow occurs in timer/counter1. tov1 is cleared by hardware when exe- cuting the corresponding interrupt handling vector. alterna- tively, tov1 is cleared by writing a logic one to the flag. when the i-bit in sreg, and toie1 (timer/counter1 over- flow interrupt enable), and tov1 are set (one), the timer/counter1 overflow interrupt is executed. in pwm mode, this bit is set when timer/counter1 changes count- ing direction at $0000. ? bit 6 - ocf1a: output compare flag 1a the ocf1a bit is set (one) when compare match occurs between the timer/counter1 and the data in ocr1a - out- put compare register 1a. ocf1a is cleared by hardware when executing the corresponding interrupt handling vec- tor. alternatively, ocf1a is cleared by writing a logic one to the flag. when the i-bit in sreg, and ocie1a (timer/counter1 compare match interrupta enable), and the ocf1a are set (one), the timer/counter1 compare match interrupt is executed. ? bit 5 - ocf1b: output compare flag 1b the ocf1b bit is set (one) when compare match occurs between the timer/counter1 and the data in ocr1b - out- put compare register 1b. ocf1b is cleared by hardware when executing the corresponding interrupt handling vec- tor. alternatively, ocf1b is cleared by writing a logic one to the flag.. when the i-bit in sreg, and ocie1b (timer/counter1 compare match interruptb enable), and the ocf1b are set (one), the timer/counter1 compare match interrupt is executed. ? bit 4 - res: reserved bit this bit is a reserved bit in the at90s8515 and always reads zero. ? bit 3 - icf1: - input capture flag 1 the icf1 bit is set (one) to flag an input capture event, indi- cating that the timer/counter1 value has been transferred to the input capture register - icr1. icf1 is cleared by hardware when executing the corresponding interrupt han- dling vector. alternatively, icf1 is cleared by writing a logic one to the flag. ? bit 2 - res: reserved bit this bit is a reserved bit in the at90s8515 and always reads zero. ? bit 1 - tov: timer/counter0 overflow flag the bit tov0 is set (one) when an overflow occurs in timer/counter0. tov0 is cleared by hardware when exe- cuting the corresponding interrupt handling vector. alterna- tively, tov0 is cleared by writing a logic one to the flag. when the sreg i-bit, and toie0 (timer/counter0 over- flow interrupt enable), and tov0 are set (one), the timer/counter0 overflow interrupt is executed. ? bit 0 - res: reserved bit this bit is a reserved bit in the at90s8515 and always reads zero. external interrupts the external interrupts are triggered by the int1 and int0 pins. observe that, if enabled, the interrupts will trigger even if the int0/int1 pins are configured as outputs. this feature provides a way of generating a software interrupt. the external interrupts can be triggered by a falling or ris- ing edge or a low level. this is set up as indicated in the specification for the mcu control register - mcucr. when the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. the external interrupts are set up as described in the spec- ification for the mcu control register - mcucr. interrupt response time the interrupt execution response for all the enabled avr interrupts is 4 clock cycles minimum. 4 clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. during this 4 clock cycle period, the program counter (2 bytes) is pushed onto the stack, and the stack pointer is decre- mented by 2. the vector is a relative jump to the interrupt routine, and this jump takes 2 clock cycles. if an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. a return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock cycles. during these 4 clock cycles, the program counter (2 bytes) is popped back from the stack, and the stack pointer is incremented by 2. when the avr exits from an interrupt, it will always return to the main program and execute one more instruc- tion before any pending interrupt is served. note that the status register - sreg - is not handled by the avr hardware, neither for interrupts nor for subrou- bit 7 6 5 4 3 2 1 0 $38 ($58) tov1 ocf1a ocifb - icf1 - tov0 - tifr read/write r/w r/w r/w r r/w r r/w r initial value 0 0 0 0 0 0 0 0 at90s8515 21 tines. for the interrupt handling routines requiring a storage of the sreg, this must be performed by user software. for interrupts triggered by events that can remain static (e.g. the output compare register1 a matching the value of timer/counter1) the interrupt flag is set when the event occurs. if the interrupt flag is cleared and the interrupt con- dition persists, the flag will not be set until the event occurs the next time. mcu control register - mcucr the mcu control register contains control bits for general mcu functions. ? bit 7 - sre: external sram enable when the sre bit is set (one), the external data sram is enabled, and the pin functions ad0-7 (port a), a8-15 (port c), wr and rd (port d) are activated as the alternate pin functions. then the sre bit overrides any pin direction set- tings in the respective data direction registers. see the sram data memory - internal and external for description of the external sram pin functions. when the sre bit is cleared (zero), the external data sram is disabled, and the normal pin and data direction settings are used. ? bit 6 - srw: external sram wait state when the srw bit is set (one), a one cycle wait state is inserted in the external data sram access cycle. when the srw bit is cleared (zero), the external data sram access is executed with the normal three-cycle scheme. see fig- ure 23: external data sram memory cycles without wait state and figure 24: external data sram memory cycles with wait state. ? bit 5 - se: sleep enable the se bit must be set (one) to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu entering the sleep mode unless it is the pro- grammers purpose, it is recommended to set the sleep enable se bit just before the execution of the sleep instruction. ? bit 4 - sm: sleep mode this bit selects between the two available sleep modes. when sm is cleared (zero), idle mode is selected as sleep mode. when sm is set (one), power down mode is selected as sleep mode. for details, refer to the paragraph sleep modes below. ? bit 3, 2 - isc11, isc10: interrupt sense control 1 bit 1 and bit 0 the external interrupt 1 is activated by the external pin int1 if the sreg i-flag and the corresponding interrupt mask in the gimsk is set. the level and edges on the external int1 pin that activate the interrupt are defined in the following table: note: when changing the isc11/isc10 bits, int1 must be dis- abled by clearing its interrupt enable bit in the gimsk register. otherwise an interrupt can occur when the bits are changed. ? bit 1, 0 - isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the external pin int0 if the sreg i-flag and the corresponding interrupt mask is set. the level and edges on the external int0 pin that activate the interrupt are defined in the following table: note: when changing the isc10/isc00 bits, int0 must be dis- abled by clearing its interrupt enable bit in the gimsk register. otherwise an interrupt can occur when the bits are changed. bit 76543210 $35 ($55) sre srw se sm isc11 isc10 isc01 isc00 mcucr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 4. interrupt 1 sense control isc11 isc10 description 00 the low level of int1 generates an interrupt request. 01reserved 10 the falling edge of int1 generates an interrupt request. 11 the rising edge of int1 generates an interrupt request. table 5. interrupt 0 sense control isc01 isc00 description 00 the low level of int0 generates an interrupt request. 01reserved 10 the falling edge of int0 generates an interrupt request. 11 the rising edge of int0 generates an interrupt request. at90s8515 22 sleep modes to enter the sleep modes, the se bit in mcucr must be set (one) and a sleep instruction must be executed. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu awakes, executes the interrupt routine, and resumes execution from the instruction following sleep. the contents of the register file, sram and i/o memory are unaltered. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. idle mode when the sm bit is cleared (zero), the sleep instruction forces the mcu into the idle mode stopping the cpu but allowing timer/counters, watchdog and the interrupt sys- tem to continue operating. this enables the mcu to wake up from external triggered interrupts as well as internal ones like timer overflow interrupt and watchdog reset. if wakeup from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd-bit in the analog comparator control and status register - acsr. this will reduce power consump- tion in idle mode. power down mode when the sm bit is set (one), the sleep instruction forces the mcu into the power down mode. in this mode, the external oscillator is stopped. the user can select whether the watchdog shall be enabled during power-down mode. if the watchdog is enabled, it will wake up the mcu when the watchdog time-out period expires. if the watchdog is dis- abled, only an external reset or an external level triggered interrupt can wake up the mcu. timer / counters the at90s8515 provides two general purpose timer/counters - one 8-bit t/c and one 16-bit t/c. the timer/counters have individual prescaling selection from the same 10-bit prescaling timer. both timer/counters can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting. the timer/counter prescaler figure 31 shows the general timer/counter prescaler. figure 31. timer/counter prescaler the four different prescaled selections are: ck/8, ck/64, ck/256 and ck/1024 where ck is the oscillator clock. for the two timer/counters, added selections as ck, external source and stop, can be selected as clock sources. at90s8515 23 the 8-bit timer/counter0 figure 32 shows the block diagram for timer/counter0. the 8-bit timer/counter0 can select clock source from ck, prescaled ck, or an external pin. in addition it can be stopped as described in the specification for the timer/counter0 control register - tccr0. the overflow status flag is found in the timer/counter insterrupt flag register - tifr. control signals are found in the timer/counter0 control register - tccr0. the interrupt enable/disable settings for timer/counter0 are found in the timer/counter interrupt mask register - timsk. when timer/counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the cpu. to assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 8-bit timer/counter0 features both a high resolution and a high accuracy usage with the lower prescaling oppor- tunities. similarly, the high prescaling opportunities make the timer/counter0 useful for lower speed functions or exact timing functions with infrequent actions. figure 32. timer/counter0 block diagram the timer/counter0 control register - tccr0 ? bits 7,6 - res: reserved bits these bits are reserved bits in the at90s8515 and always read zero. ? bits 2,1,0 - cs02, cs01, cs00: clock select0, bit 2,1 and 0 the clock select0 bits 2,1 and 0 define the prescaling source of timer0. bit 7 6 5 4 3 2 1 0 $33 ($53) - - - - - cs02 cs01 cs00 tccr0 read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 at90s8515 24 the stop condition provides a timer enable/disable func- tion. the ck down divided modes are scaled directly from the ck oscillator clock. if the external pin modes are used, the corresponding setup must be performed in the actual data direction control register (cleared to zero gives an input pin). the timer counter 0 - tcnt0 the timer/counter0 is realized as an up-counter with read and write access. if the timer/counter0 is written and a clock source is present, the timer/counter0 continues counting in the clock cycle following the write operation. table 6. clock 0 prescale select cs02 cs01 cs00 description 0 0 0 stop, the timer/counter0 is stopped. 001ck 010ck / 8 011ck / 64 100ck / 256 101ck / 1024 1 1 0 external pin t0, falling edge 1 1 1 external pin t0, rising edge bit 76543210 $32 ($52) msb lsb tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 at90s8515 25 the 16-bit timer/counter1 figure 33 shows the block diagram for timer/counter1. figure 33. timer/counter1 block diagram the 16-bit timer/counter1 can select clock source from ck, prescaled ck, or an external pin. in addition it can be stopped as described in the specification for the timer/counter1 control registers - tccr1a and tccr1b. the different status flags (overflow, compare match and capture event) and control signals are found in the timer/counter1 control registers - tccr1a and tccr1b. the interrupt enable/disable settings for timer/counter1 are found in the timer/counter interrupt mask register - timsk. when timer/counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the cpu. to assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal cpu clock period. the external clock signal is sampled on the rising edge of the internal cpu clock. the 16-bit timer/counter1 features both a high resolution and a high accuracy usage with the lower prescaling oppor- tunities. similarly, the high prescaling opportunities makes the timer/counter1 useful for lower speed functions or exact timing functions with infrequent actions. the timer/counter1 supports two output compare func- tions using the output compare register 1 a and b - ocr1a and ocr1b as the data sources to be compared to the timer/counter1 contents. the output compare func- tions include optional clearing of the counter on comparea match, and actions on the output compare pins on both compare matches. timer/counter1 can also be used as a 8, 9 or 10-bit pulse with modulator. in this mode the counter and the ocr1a/ocr1b registers serve as a dual glitch-free stand- alone pwm with centered pulses. refer to page 33 for a detailed description on this function. the input capture function of timer/counter1 provides a capture of the timer/counter1 contents to the input cap- ture register - icr1, triggered by an external event on the input capture pin - icp. the actual capture event settings at90s8515 26 are defined by the timer/counter1 control register - tccr1b. in addition, the analog comparator can be set to trigger the input capture. refer to the section, the analog comparator, for details on this. the icp pin logic is shown in figure 34. figure 34. icp pin schematic diagram if the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over 4 samples before the capture is activated. the input pin signal is sam- pled at xtal clock frequency. the timer/counter1 control register a - tccr1a ? bits 7,6 - com1a1, com1a0: compare output mode1a, bits 1 and 0 the com1a1 and com1a0 control bits determine any out- put pin action following a compare match in timer/counter1. any output pin actions affect pin oc1a - output comparea pin 1. since this is an alternative func- tion to an i/o port, the corresponding direction control bit must be set (one) to control an output pin. the control con- figuration is shown in table 7. ? bits 5,4 - com1b1, com1b0: compare output mode1b, bits 1 and 0 the com1b1 and com1b0 control bits determine any out- put pin action following a compare match in timer/counter1. any output pin actions affect pin oc1b - output compareb. the following control configuration is given: x = a or b in pwm mode, these bits have a different function. refer to table 11 for a detailed description. when changing the com1x1/com1x0 bits, output com- pare interrupts 1 must be disabled by clearing their inter- rupt enable bits in the timsk register. otherwise an interrupt can occur when the bits are changed. ? bits 3..2 - res: reserved bits these bits are reserved bits in the at90s8515 and always read zero. ? bits 1..0 - pwm11, pwm10: pulse width modulator select bits these bits select pwm operation of timer/counter1 as specified in table 8. this mode is described on page 29. bit 7 6 5 4 3 2 1 0 $2f ($4f) com1a1 com1a0 com1b1 com1b0 - - pwm11 pwm10 tccr1a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 7. compare 1 mode select com1x1 com1x0 description 00 timer/counter1 disconnected from output pin oc1x 0 1 toggle the oc1x output line. 1 0 clear the oc1x output line (to zero). 1 1 set the oc1x output line (to one). table 8. pwm mode select pwm11 pwm10 description 00 pwm operation of timer/counter1 is disabled 0 1 timer/counter1 is an 8-bit pwm 1 0 timer/counter1 is a 9-bit pwm 1 1 timer/counter1 is a 10-bit pwm at90s8515 27 the timer/counter1 control register b - tccr1b ? bit 7 - icnc1: input capture1 noise canceler (4 cks) when the icnc1 bit is cleared (zero), the input capture trig- ger noise canceler function is disabled. the input capture is triggered at the first rising/falling edge sampled on the icp - input capture pin - as specified. when the icnc1 bit is set (one), four successive samples are measures on the icp - input capture pin, and all samples must be high/low accord- ing to the input capture trigger specification in the ices1 bit. the actual sampling frequency is xtal clock fre- quency. ? bit 6 - ices1: input capture1 edge select while the ices1 bit is cleared (zero), the timer/counter1 contents are transferred to the input capture register - icr1 - on the falling edge of the input capture pin - icp. while the ices1 bit is set (one), the timer/counter1 con- tents are transferred to the input capture register - icr1 - on the rising edge of the input capture pin - icp. ? bits 5, 4 - res: reserved bits these bits are reserved bits in the at90s8515 and always read zero. ? bit 3 - ctc1: clear timer/counter1 on compare match when the ctc1 control bit is set (one), the timer/counter1 is reset to $0000 in the clock cycle after a comparea match. if the ctc1 control bit is cleared, timer/counter1 continues counting and is unaffected by a compare match. since the compare match is detected in the cpu clock cycle following the match, this function will behave differ- ently when a prescaling higher than 1 is used for the timer. when a prescaling of 1 is used, and the comparea register is set to c, the timer will count as follows i ctc1 is set: ... | c-1 | c | c+1 | 0 | 1 | ... when the prescaler is set to divide by 8, the timer will count like this: ... | c-1, c-1, c-1, c-1, c-1, c-1, c-1, c-1 | c, c, c, c, c, c, c, c | c+1, 0, 0, 0, 0, 0, 0, 0, 0 | ... in pwm mode, this bit has no effect. ? bits 2,1,0 - cs12, cs11, cs10: clock select1, bit 2,1 and 0 the clock select1 bits 2,1 and 0 define the prescaling source of timer/counter1. the stop condition provides a timer enable/disable func- tion. the ck down divided modes are scaled directly from the ck oscillator clock. if the external pin modes are used, the corresponding setup must be performed in the actual direction control register (cleared to zero gives an input pin). the timer/counter1 - tcnt1h and tcnt1l this 16-bit register contains the prescaled value of the 16- bit timer/counter1. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is performed using an 8-bit temporary register (temp). this temporary register is also used when accessing ocr1a, ocr1b and icr1. if the main program and also interrupt routines perform access to registers using temp, interrupts must be dis- abled during access from the main program. ? tcnt1 timer/counter1 write: when the cpu writes to the high byte tcnt1h, the written data is placed in the temp register. next, when the cpu writes the low byte tcnt1l, this byte of data is combined with the byte data in the temp register, bit 7 6 5 4 3 2 1 0 $2e ($4e) icnc1 ices1 - - ctc1 cs12 cs11 cs10 tccr1b read/write r/w r/w r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 9. clock 1 prescale select cs12 cs11 cs10 description 0 0 0 stop, the timer/counter1 is stopped. 001ck 0 1 0 ck / 8 011ck / 64 1 0 0 ck / 256 1 0 1 ck / 1024 1 1 0 external pin t1, falling edge 1 1 1 external pin t1, rising edge bit 151413121110 9 8 $2d ($4d) msb tcnt1h $2c ($4c) lsb tcnt1l 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00000000 at90s8515 28 and all 16 bits are written to the tcnt1 timer/counter1 register simultaneously. conse- quently, the high byte tcnt1h must be accessed first for a full 16-bit register write operation. ? tcnt1 timer/counter1 read: when the cpu reads the low byte tcnt1l, the data of the low byte tcnt1l is sent to the cpu and the data of the high byte tcnt1h is placed in the temp register. when the cpu reads the data in the high byte tcnt1h, the cpu receives the data in the temp reg- ister. consequently, the low byte tcnt1l must be accessed first for a full 16-bit register read operation. the timer/counter1 is realized as an up or up/down (in pwm mode) counter with read and write access. if timer/counter1 is written to and a clock source is selected, the timer/counter1 continues counting in the timer clock cycle after it is preset with the written value. timer/counter1 output compare register - ocr1ah and ocr1al timer/counter1 output compare register - ocr1bh and ocr1bl the output compare registers are 16-bit read/write regis- ters. the timer/counter1 output compare registers contain the data to be continuously compared with timer/counter1. actions on compare matches are specified in the timer/counter1 control and status register.a compare match does only occur if timer/counter1 counts to the ocr value. a software write that sets tcnt1 and ocr1a or ocr1b to the same value does not generate a compare match. a compare match will set the compare interrupt flag in the cpu clock cycle following the compare event. since the output compare registers - ocr1a and ocr1b - are 16-bit registers, a temporary register temp is used when ocr1a/b are written to ensure that both bytes are updated simultaneously. when the cpu writes the high byte, ocr1ah or ocr1bh, the data is temporarily stored in the temp register. when the cpu writes the low byte, ocr1al or ocr1bl, the temp register is simultaneously written to ocr1ah or ocr1bh. consequently, the high byte ocr1ah or ocr1bh must be written first for a full 16-bit register write operation. the temp register is also used when accessing tcnt1, and icr1. if the main program and also interrupt routines perform access to registers using temp, interrupts must be disabled during access from the main program. bit 151413121110 9 8 $2b ($4b) msb ocr1ah $2a ($4a) lsb ocr1al 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00000000 bit 151413121110 9 8 $29 ($49) msb ocr1bh $28 ($48) lsb ocr1bl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 00000000 at90s8515 29 the timer/counter1 input capture register - icr1h and icr1l the input capture register is a 16-bit read-only register. when the rising or falling edge (according to the input cap- ture edge setting - ices1) of the signal at the input capture pin - icp - is detected, the current value of the timer/counter1 is transferred to the input capture register - icr1. at the same time, the input capture flag - icf1 - is set (one). since the input capture register - icr1 - is a 16-bit regis- ter, a temporary register temp is used when icr1 is read to ensure that both bytes are read simultaneously. when the cpu reads the low byte icr1l, the data is sent to the cpu and the data of the high byte icr1h is placed in the temp register. when the cpu reads the data in the high byte icr1h, the cpu receives the data in the temp regis- ter. consequently, the low byte icr1l must be accessed first for a full 16-bit register read operation. the temp register is also used when accessing tcnt1, ocr1a and ocr1b. if the main program and also interrupt routines perform access to registers using temp, inter- rupts must be disabled during access from the main pro- gram. timer/counter1 in pwm mode when the pwm mode is selected, timer/counter1 and the output compare register1a - ocr1a and the output compare register1b - ocr1b, form a dual 8, 9 or 10-bit, free-running, glitch-free and phase correct pwm with out- puts on the pd5(oc1a) and oc1b pins. timer/counter1 acts as an up/down counter, counting up from $0000 to top (see table 10) , when it turns and counts down again to zero before the cycle is repeated. when the counter value matches the contents of the 10 least significant bits of ocr1a or ocr1b, the pd5(oc1a)/oc1b pins are set or cleared according to the settings of the com1a1/com1a0 or com1b1/com1b0 bits in the timer/counter1 control register tccr1a. refer to table 11 for details. note: x = a or b note that in the pwm mode, the 10 least significant ocr1a/ocr1b bits, when written, are transferred to a temporary location. they are latched when timer/counter1 reaches the value top. this prevents the occurrence of odd-length pwm pulses (glitches) in the event of an unsyn- chronized ocr1a/ocr1b write. see figure 35 for an example. bit 151413121110 9 8 $25 ($45) msb icr1h $24 ($44) lsb icr1l 76543210 read/write rrrrrrrr rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 table 10. timer top values and pwm frequency pwm resolution timer top value frequency 8-bit $00ff (255) f tc1 /510 9-bit $01ff (511) f tc1 /1022 10-bit $03ff(1023) f tc1 /2046 table 11. compare1 mode select in pwm mode com1x1 com1x0 effect on ocx1 0 0 not connected 0 1 not connected 10 cleared on compare match, upcounting. set on compare match, downcounting (non-inverted pwm). 11 cleared on compare match, downcounting. set on compare match, upcounting (inverted pwm). at90s8515 30 figure 35. effects on unsynchronized ocr1 latching during the time between the write and the latch operation, a read from ocr1a or ocr1b will read the contents of the temporary location. this means that the most recently writ- ten value always will read out of ocr1a/b when ocr1 contains $0000 or top, the output oc1a/oc1b is held low or high according to the settings of com1a1/com1a0 or com1b1/com1b0. this is shown in table 12: note: x = a or b in pwm mode, the timer overflow flag1, tov1, is set when the counter changes direction at $0000. timer over- flow interrupt1 operates exactly as in normal timer/counter mode, i.e. it is executed when tov1 is set provided that timer overflow interrupt1 and global interrupts are enabled. this does also apply to the timer output compare1 flags and interrupts. the watchdog timer the watchdog timer is clocked from a separate on-chip oscillator which runs at 1mhz this is the typical value at v cc = 5v. see characterization data for typical values at other v cc levels. by controlling the watchdog timer pres- caler, the watchdog reset interval can be adjusted from 16k to 2,048k cycles (nominally 16 - 2048 ms). the wdr - watchdog reset - instruction resets the watchdog timer. eight different clock cycle periods can be selected to deter- mine the reset period. if the reset period expires without another watchdog reset, the at90s8515 resets and exe- cutes from the reset vector. for timing details on the watchdog reset, refer to page 18. to prevent unintentional disabling of the watchdog, a spe- cial turn-off secuence must be followed when the watchdog is disabled.refer to the description of the watchdog timer control register for details. figure 36. watchdog timer table 12. pwm outputs ocr1x = $0000 or top com1x1 com1x0 ocr1x output oc1x 1 0 $0000 l 10top h 1 1 $0000 h 11top l at90s8515 31 the watchdog timer control register - wdtcr ? bits 7..5 - res: reserved bits these bits are reserved bits in the at90s8515 and will always read as zero. ? bit 4 - wdtoe: watch dog turn-off enable this bit must be set (one) when the wde bit is cleared. otherwise, the watchdog will not be disabled. once set, hardware will clear this bit to zero after four clock cycles. refer to the description of the wde bit for a watchdog dis- able procedure. ? bit 3 - wde: watch dog enable when the wde is set (one) the watchdog timer is enabled, and if the wde is cleared (zero) the watchdog timer function is disabled. wde can only be cleared if the wdtoe bit is set(one). to disable an enabled watchdog timer, the following procedure must be followed: 1. in the same operation, write a logical one to wdtoe and wde. a logcal one must be written to wde even though it is set to one before the disable operation starts. 2. within the next four clock cycles, write a logical 0 to wde. this disables the watchdog. ? bits 2..0 - wdp2, wdp1, wdp0: watch dog timer prescaler 2, 1 and 0 the wdp2, wdp1 and wdp0 bits determine the watch- dog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corre- sponding timeout periods are shown in table 13. eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time is in the range of 2.5 - 4ms, depend- ing on the v cc voltages. a self-timing function, however, lets the user software detect when the next byte can be written. if the user code contains code that writes the eeprom, some precaution must be taken. in heavily fil- tered power supplies, v cc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. cpu operation under these con- ditions is likely cause the program counter to perform unin- tentional jumps and eventually execute the eeprom write code. to secure eeprom integrity, the user is advised to use an external under-voltage reset circuit in this case. in order to prevent unintentional eeprom writes, a spe- cific write procedure must be followed. refer to the descrip- tion of the eeprom control register for details on this. when the eeprom is read or written, the cpu is halted for two clock cycles before the next instruction is executed. bit 76543210 $21 ($41) - - - wdtoe wde wdp2 wdp1 wdp0 wdtcr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 13. watch dog timer prescale select wdp2 wdp1 wdp0 timeout period 0 0 0 16k cycles 0 0 1 32k cycles 0 1 0 64k cycles 0 1 1 128k cycles 1 0 0 256k cycles 1 0 1 512k cycles 1 1 0 1,024k cycles 1 1 1 2,048k cycles at90s8515 32 the eeprom address register - eearh and eearl the eeprom address registers - eearh and eearl specify the eeprom address in the 512 bytes eeprom space. the eeprom data bytes are addressed linearly between 0 and 512. the eeprom data register - eedr ? bits 7..0 - eedr7..0: eeprom data for the eeprom write operation, the eedr register con- tains the data to be written to the eeprom in the address given by the eear register. for the eeprom read opera- tion, the eedr contains the data read out from the eeprom at the address given by eear. the eeprom control register - eecr ? bit 7..3 - res: reserved bits these bits are reserved bits in the at90s8515 and will always read as zero. ? bit 2 - eemwe: eeprom master write enable the eemwe bit determines whether setting eewe to one causes the eeprom to be written. when eemwe is set(one) setting eewe will write data to the eeprom at the selected address if eemwe is zero, setting eewe will have no effect. when eemwe has been set (one) by soft- ware, hardware clears the bit to zero after four clock cycles. see the description of the eewe bit for a eeprom write procedure. ? bit 1 - eewe: eeprom write enable the eeprom write enable signal eewe is the write strobe to the eeprom. when address and data are cor- rectly set up, the eewe bit must be set to write the value into the eeprom. the eemwe bit must be set when the logical one is written to eewe, otherwise no eeprom write takes place. the following procedure should be fol- lowed when writing the eeprom (the order of steps 2 and 3 is unessential): 1. wait until eewe becomes zero. 2. write new eeprom address to eearl and eearh (optional) 3. write new eeprom data to eedr (optional) 4. write a logical one to the eemwe bit in eecr 5. within four clock cycles after setting eemwe, write a logical one to eewe. when the write access time (typically 2.5 ms at v cc = 5v or 4 ms at v cc = 2.7v) has elapsed, the eewe bit is cleared (zero) by hardware. the user software can poll this bit and wait for a zero before writing the next byte. when eewe has been set, the cpu is halted for two cycles before the next instruction is executed. ? bit 0 - eere: eeprom read enable the eeprom read enable signal eere is the read strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be set. when the eere bit is cleared (zero) by hardware, requested data is found in the eedr register. the eeprom read access takes one instruction and there is no need to poll the eere bit. when eere has been set, the cpu is halted for two cycles before the next instruction is executed. the user should poll the eewe bit before starting the read operation. if a write operation is in progress when new data or address is written to the eeprom i/o registers, the write operation will be interrupted, and the result is unde- fined. bit 151413121110 9 8 $1f ($3f) - - - - - - - eear8 eearh $1e ($3e) eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 8 0 0 0 0 0 0 0 80000000 bit 76543210 $1d ($3d) msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $1c ($3c) - - - - - eemwe eewe eere eecr read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 at90s8515 33 the serial peripheral interface - spi the serial peripheral interface (spi) allows high-speed synchronous data transfer between the at90s8515 and peripheral devices or between several at90s8515 devices. the at90s8515 spi features include the following: ? full-duplex, 3-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? four programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wakeup from idle mode (slave mode only) figure 37. spi block diagram the interconnection between master and slave cpus with spi is shown in figure 38. the pb7(sck) pin is the clock output in the master mode and is the clock input in the slave mode. writing to the spi data register of the master cpu starts the spi clock generator, and the data written shifts out of the pb5(mosi) pin and into the pb5(mosi) pin of the slave cpu. after shifting one byte, the spi clock gen- erator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the slave select input, pb4(ss ), is set low to select an individual spi device as a slave. the two shift registers in the master and the slave can be considered as one distributed 16-bit circular shift register. this is shown in figure 38. when data is shifted from the master to the slave, data is also shifted in the opposite direction, simultaneously. this means that during one shift cycle, data in the master and the slave are inter- changed. at90s8515 34 figure 38. spi master-slave interconnection the system is single buffered in the transmit direction and double buffered in the receive direction. this means that characters to be transmitted cannot be written to the spi data register before the entire shift cycle is completed. when receiving data, however, a received character must be read from the spi data register before the next charac- ter has been completely shifted in. otherwise, the first char- acter is lost. when the spi is enabled, the data direction of the mosi, miso, sck and ss pins is overriden according to the fol- lowing table: ss pin functionality when the spi is configured as a master (mstr in spcr is set), the user can determine the direction of the ss pin. if ss is configured as an output, the pin is a general output pin which does not affect the spi system. if ss is config- ured as an input, it must be hold high to ensure master spi operation. if, in master mode, the ss pin is input, and is driven low by peripheral circuitry, the spi system inter- pretes this as another master selecting the spi as a slave and starting to send data to it. to avoid bus contention, the spi system takes the following actions: 1. the mstr bit in spcr is cleared and the spi sys- tem becomes a slave. as a result of the spi becom- ing a slave, the mosi and sck pins become inputs. 2. the spif flag in spsr is set, and if the spi inter- rupt is enabled, the interrupt routine will be exe- cuted. thus, when interrupt-driven spi transmittal is used in mas- ter mode, and there exists a possibility that ss is driven low, the interrupt should always check that the mstr bit is still set. once the mstr bit has been cleared by a slave select, it must be set by the user. when the spi is configured as a slave, the ss pin is always input. when ss is held low, the spi is activated and miso becomes an output if configured so by the user. all other pins are inputs. when ss is driven high, all pins are inputs, and the spi is passive, which means that it will not receive incoming data. data modes there are four combinations of sck phase and polarity with respect to serial data, which are determined by control bits cpha and cpol. the spi data transfer formats are shown in figure 39 and figure 40. table 14. spi pin overrides pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input at90s8515 35 figure 39. spi transfer format with cpha = 0 figure 40. spi transfer format with cpha = 1 the spi control register - spcr ? bit 7 - spie: spi interrupt enable this bit causes setting of the spif bit in the spsr register to execute the spi interrupt provided that global interrupts are enabled. ? bit 6 - spe: spi enable when the spe bit is set (one), the spi is enabled. this bit must be set to enable any spi operations. ? bit 5 - dord: data order when the dord bit is set (one), the lsb of the data word is transmitted first. when the dord bit is cleared (zero), the msb of the data word is transmitted first. ? bit 4 - mstr: master/slave select this bit selects master spi mode when set (one), and slave spi mode when cleared (zero). if ss is configured as an input and is driven low whil mstr is set, mstr will be cleared, and spif in spsr will become set. the user will then have to set mstr to re-enable spi master mode. ? bit 3 - cpol: clock polarity when this bit is set (one), sck is high when idle. when cpol is cleared (zero), sck is low when idle. refer to fig- ure 39 and figure 40 for additional information. ? bit 2 - cpha: clock phase refer to figure 39 or figure 40 for the functionality of this bit. ? bits 1,0 - spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device config- ured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator clock frequency f cl is shown in the following table: bit 76543210 $0d ($2d) spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 1 0 0 table 15. relationship between sck and the oscillator frequency spr1 spr0 sck frequency 00 f cl / 4 01 f cl / 16 10 f cl / 64 11 f cl / 128 at90s8515 36 the spi status register - spsr ? bit 7 - spif: spi interrupt flag when a serial transfer is complete, the spif bit is set (one) and an interrupt is generated if spie in spcr is set (one) and global interrupts are enabled. if ss is an input and is driven low when the spi is in master mode, this will also set the spif flag. spif is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status regis- ter with spif set (one), then accessing the spi data regis- ter (spdr). ? bit 6 - wcol: write collision flag the wcol bit is set if the spi data register (spdr) is writ- ten during a data transfer. during data transfer, the result of reading the spdr register may be incorrect, and writing to it will have no effect. the wcol bit (and the spif bit) are cleared (zero) by first reading the spi status register with wcol set (one), and then accessing the spi data regis- ter. ? bit 5..0 - res: reserved bits these bits are reserved bits in the at90s8515 and will always read as zero. the spi interface on the at90s8515 is also used for pro- gram memory and eeprom downloading or uploading. see page 62 for serial programming and verification. the spi data register - spdr the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the register initiates data transmission. reading the register causes the shift register receive buffer to be read. bit 76543210 $0e ($2e) spif wcol - - - - - - spsr read/write rrrrrrrr initial value 0 0 0 0 0 0 0 0 bit 76543210 $0f ($2f) msb lsb spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 at90s8515 37 the uart the at90s8515 features a full duplex universal asynchronous receiver and transmitter (uart). the main features are: ? baud rate generator generates any baud rate ? high baud rates at low xtal frequencies ? 8 or 9 bits data ? noise filtering ? overrun detection ? framing error detection ? false start bit detection ? three separate interrupts on tx complete, tx data register empty and rx complete data transmission a block schematic of the uart transmitter is shown in figure 41. figure 41. uart transmitter data transmission is initiated by writing the data to be transmitted to the uart i/o data register, udr. data is transferred from udr to the transmit shift register when: ? a new character has been written to udr after the stop bit from the previous character has been shifted out. the shift register is loaded immediately. ? a new character has been written to udr before the stop bit from the previous character has been shifted out. the shift register is loaded when the stop bit of the character currently being transmitted has been shifted out. if the 10(11)-bit transmitter shift register is empty or when, data is transferred from udr to the shift register. at this time the udre (uart data register empty) bit in the uart status register, usr, is set. when this bit is set (one), the uart is ready to receive the next character. at the same time as the data is transferred from udr to the 10(11)-bit shift register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). if 9 bit data word is selected (the chr9 bit in the uart control register, ucr is set), the txb8 bit in ucr is transferred to bit 9 in the transmit shift register. at90s8515 38 on the baud rate clock following the transfer operation to the shift register, the start bit is shifted out on the txd pin. then follows the data, lsb first. when the stop bit has been shifted out, the shift register is loaded if any new data has been written to the udr during the transmission. dur- ing loading, udre is set. if there is no new data in the udr register to send when the stop bit is shifted out, the udre flag will remain set until udr is written again. when no new data has been written, and the stop bit has been present on txd for one bit length, the tx complete flag, txc, in usr is set. the txen bit in ucr enables the uart transmitter when set (one). when this bit is cleared (zero), the pd1 pin can be used for general i/o. when txen is set, the uart transmitter will be connected to pd1, which is forced to be an output pin regardless of the setting of the ddd1 bit in ddrd. data reception figure 42 shows a block diagram of the uart receiver. figure 42. uart receiver the receiver front-end logic samples the signal on the rxd pin at a frequency 16 times the baud rate. while the line is idle, one single sample of logical zero will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated. let sample 1 denote the first zero- sample. following the 1 to 0-transition, the receiver sam- ples the rxd pin at samples 8, 9 and 10. if two or more of these three samples are found to be logical ones, the start bit is rejected as a noise spike and the receiver starts look- ing for the next 1 to 0-transition. if however, a valid start bit is detected, sampling of the data bits following the start bit is performed. these bits are also sampled at samples 8, 9 and 10. the logical value found in at least two of the three samples is taken as the bit value. all bits are shifted into the transmitter shift register as they are sampled. sampling of an incoming character is shown in figure 43. at90s8515 39 figure 43. sampling received data when the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. if two or more samples are logical zeros, the framing error (fe) flag in the uart status register (usr) is set. before reading the udr register, the user should always check the fe bit to detect framing errors. whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to udr and the rxc flag in usr is set. udr is in fact two physi- cally separate registers, one for transmitted data and one for received data. when udr is read, the receive data register is accessed, and when udr is written, the trans- mit data register is accessed. if 9 bit data word is selected (the chr9 bit in the uart control register, ucr is set), the rxb8 bit in ucr is loaded with bit 9 in the transmit shift register when data is transferred to udr. if, after having received a character, the udr register has not been read since the last receive, the overrun (or) flag in ucr is set. this means that the last data byte shifted into to the shift register could not be transferred to udr and has been lost. the or bit is buffered, and is updated when the valid data byte in udr is read. thus, the user should always check the or bit after reading the udr reg- ister in order to detect any overruns. when the rxen bit in the ucr register is cleared (zero), the receiver is disabled. this means that the pd0 pin can be used as a general i/o pin. when rxen is set, the uart receiver will be connected to pd0, which is forced to be an input pin regardless of the setting of the ddd0 bit in ddrd. when pd0 is forced to input by the uart, the portd0 bit can still be used to control the pull-up resistor on the pin. uart control the uart i/o data register - udr the udr register is actually two physically separate regis- ters sharing the same i/o address. when writing to the reg- ister, the uart transmit data register is written. when reading from udr, the uart receive data register is read. the uart status register - usr the usr register is a read-only register providing informa- tion on the uart status. ? bit 7 - rxc: uart receive complete this bit is set (one) when a received character is trans- ferred from the receiver shift register to udr. the bit is set regardless of any detected framing errors. when the rxcie bit in ucr is set, the uart receive complete interrupt will be executed when rxc is set(one). rxc is cleared by reading udr. when interrupt-driven data recep- tion is used, the uart receive complete interrupt routine must read udr in order to clear rxc, otherwise a new interrupt will occur once the interrupt routine terminates. ? bit 6 - txc : uart transmit complete this bit is set (one) when the entire character (including the stop bit) in the transmit shift register has been shifted out and no new data has been written to udr. this flag is especially useful in half-duplex communications interfaces, where a transmitting application must enter receive mode and free the communications bus immediately after com- pleting the transmission. when the txcie bit in ucr is set, setting of txc causes the uart transmit complete interrupt to be executed. txc is cleared by hardware when executing the corre- sponding interrupt handling vector. alternatively, the txc bit is cleared (zero) by writing a logical one to the bit. ? bit 5 - udre: uart data register empty this bit is set (one) when a character written to udr is transferred to the transmit shift register. setting of this bit indicates that the transmitter is ready to receive a new character for transmission. bit 76543210 $0c ($2c) msb lsb udr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $0b ($2b) rxc txc udre fe or - - - usr read/write r r/w r r r r r r initial value 0 0 1 0 0 0 0 0 at90s8515 40 when the udrie bit in ucr is set, the uart transmit complete interrupt to be executed as long as udre is set. udre is cleared by writing udr. when interrupt-driven data transmittal is used, the uart data register empty interrupt routine must write udr in order to clear udre, otherwise a new interrupt will occur once the interrupt rou- tine terminates. udre is set (one) during reset to indicate that the transmit- ter is ready. ? bit 4 - fe: framing error this bit is set if a framing error condition is detected, i.e. when the stop bit of an incoming character is zero. the fe bit is cleared when the stop bit of received data is one. ? bit 3 - or: overrun this bit is set if an overrun condition is detected, i.e. when a character already present in the udr register is not read before the next character has been shifted into the receiver shift register. the or bit is buffered, which means that it will be set once the valid data still in udre is read. the or bit is cleared (zero) when data is received and transferred to udr. ? bits 2..0 - res: reserved bits these bits are reserved bits in the at90s8515 and will always read as zero. the uart control register - ucr ? bit 7 - rxcie: rx complete interrupt enable when this bit is set (one), a setting of the rxc bit in usr will cause the receive complete interrupt routine to be executed provided that global interrupts are enabled. ? bit 6 - txcie: tx complete interrupt enable when this bit is set (one), a setting of the txc bit in usr will cause the transmit complete interrupt routine to be executed provided that global interrupts are enabled. ? bit 5 - udrie: uart data register empty interrupt enable when this bit is set (one), a setting of the udre bit in usr will cause the uart data register empty interrupt routine to be executed provided that global interrupts are enabled. ? bit 4 - rxen: receiver enable this bit enables the uart receiver when set (one). when the receiver is disabled, the txc, or and fe status flags cannot become set. if these flags are set, turning off rxen does not cause them to be cleared. ? bit 3 - txen: transmitter enable this bit enables the uart transmitter when set (one). when disabling the transmitter while transmitting a charac- ter, the transmitter is not disabled before the character in the shift register plus any following character in udr has been completely transmitted. ? bit 2 - chr9: 9 bit characters when this bit is set (one) transmitted and received charac- ters are 9 bit long plus start and stop bits. the 9th bit is read and written by using the rxb8 and txb8 bits in ucr, respectively. the 9th data bit can be used as an extra stop bit or a parity bit. ? bit 1 - rxb8: receive data bit 8 when chr9 is set (one), rxb8 is the 9th data bit of the received character. ? bit 0 - txb8: transmit data bit 8 when chr9 is set (one), txb8 is the 9th data bit in the character to be transmitted. the baud rate generator the baud rate generator is a frequency divider which gen- erates baud-rates according to the following equation: ? baud = baud-rate ? fck= crystal clock frequency ? ubrr= contents of the uart baud rate register, ubrr (0-255) for standard crystal frequencies, the most commonly used baud rates can be generated by using the ubrr settings in table 16. ubrr values which yield an actual baud rate dif- fering less than 2% from the target baud rate, are bolded in the table. bit 76543210 $0a ($2a) rxcie txcie udrie rxen txen chr9 rxb8 txb8 ucr read/write r/w r/w r/w r/w r/w r/w r w initial value 0 0 0 0 0 0 0 0 baud f ck 16(ubrr 1) + ------------------------------------ - = at90s8515 41 table 16. ubrr settings at various crystal frequencies the uart baud rate register - ubrr the ubrr register is an 8-bit read/write register which specifies the uart baud rate according to the equation on the previous page. baud rate 1mhz %error 1.8432 mhz %error 2mhz %error 2.4576 mhz %error 2400 ubrr= 25 0.2 ubrr= 47 0.0 ubrr= 51 0.2 ubrr= 63 0.0 4800 ubrr= 12 0.2 ubrr= 23 0.0 ubrr= 25 0.2 ubrr= 31 0.0 9600 ubrr= 6 7.5 ubrr= 11 0.0 ubrr= 12 0.2 ubrr= 15 0.0 14400 ubrr= 3 7.8 ubrr= 70.0 ubrr= 8 3.7 ubrr= 10 3.1 19200 ubrr= 2 7.8 ubrr= 50.0 ubrr= 6 7.5 ubrr= 70.0 28800 ubrr= 1 7.8 ubrr= 30.0 ubrr= 3 7.8 ubrr= 4 6.3 38400 ubrr= 1 22.9 ubrr= 20.0 ubrr= 2 7.8 ubrr= 30.0 57600 ubrr= 0 7.8 ubrr= 10.0 ubrr= 1 7.8 ubrr= 2 12.5 76800 ubrr= 0 22.9 ubrr= 1 33.3 ubrr= 1 22.9 ubrr= 10.0 115200 ubrr= 0 84.3 ubrr= 00.0 ubrr= 0 7.8 ubrr= 0 25.0 baud rate 3.2768 mhz %error 3.6864 mhz %error 4mhz %error 4.608 mhz %error 2400 ubrr= 84 0.4 ubrr= 95 0.0 ubrr= 103 0.2 ubrr= 119 0.0 4800 ubrr= 42 0.8 ubrr= 47 0.0 ubrr= 51 0.2 ubrr= 59 0.0 9600 ubrr= 20 1.6 ubrr= 23 0.0 ubrr= 25 0.2 ubrr= 29 0.0 14400 ubrr= 13 1.6 ubrr= 15 0.0 ubrr= 16 2.1 ubrr= 19 0.0 19200 ubrr= 10 3.1 ubrr= 11 0.0 ubrr= 12 0.2 ubrr= 14 0.0 28800 ubrr= 61.6 ubrr= 70.0 ubrr= 8 3.7 ubrr= 90.0 38400 ubrr= 4 6.3 ubrr= 50.0 ubrr= 6 7.5 ubrr= 7 6.7 57600 ubrr= 3 12.5 ubrr= 30.0 ubrr= 3 7.8 ubrr= 40.0 76800 ubrr= 2 12.5 ubrr= 20.0 ubrr= 2 7.8 ubrr= 3 6.7 115200 ubrr= 1 12.5 ubrr= 10.0 ubrr= 1 7.8 ubrr= 2 20.0 baud rate 7.3728 mhz %error 8mhz %error 9.216 mhz %error 11.059 mhz %error 2400 ubrr= 191 0.0 ubrr= 207 0.2 ubrr= 239 0.0 ubrr= 287 - 4800 ubrr= 95 0.0 ubrr= 103 0.2 ubrr= 119 0.0 ubrr= 143 0.0 9600 ubrr= 47 0.0 ubrr= 51 0.2 ubrr= 59 0.0 ubrr= 71 0.0 14400 ubrr= 31 0.0 ubrr= 34 0.8 ubrr= 39 0.0 ubrr= 47 0.0 19200 ubrr= 23 0.0 ubrr= 25 0.2 ubrr= 29 0.0 ubrr= 35 0.0 28800 ubrr= 15 0.0 ubrr= 16 2.1 ubrr= 19 0.0 ubrr= 23 0.0 38400 ubrr= 11 0.0 ubrr= 12 0.2 ubrr= 14 0.0 ubrr= 17 0.0 57600 ubrr= 70.0 ubrr= 8 3.7 ubrr= 90.0 ubrr= 11 0.0 76800 ubrr= 50.0 ubrr= 6 7.5 ubrr= 7 6.7 ubrr= 80.0 115200 ubrr= 30.0 ubrr= 3 7.8 ubrr= 40.0 ubrr= 50.0 bit 76543210 $09 ($29) msb lsb ubrr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 at90s8515 42 the analog comparator the analog comparator compares the input values on the positive pin pb2 (ain0) and negative pin pb3 (ain1). when the voltage on the positive pin pb2 (ain0) is higher than the voltage on the negative pin pb3 (ain1), the ana- log comparator output, aco is set (one). the compara- tors output can be set to trigger the timer/counter1 input capture function. in addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator. the user can select interrupt triggering on comparator out- put rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 44 . figure 44. analog comparator block diagram the analog comparator control and status register - acsr ? bit 7 - acd: analog comparator disable when this bit is set(one), the power to the analog compara- tor is switched off. this bit can be set at any time to turn off the analog comparator. this will reduce power consump- tion in active and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clear- ing the acie bit in acsr. otherwise an interrupt can occur when the bit is changed. ? bit 6 - res: reserved bit this bit is a reserved bit in the at90s8515 and will always read as zero. ? bit 5 - aco: analog comparator output aco is directly connected to the comparator output. ? bit 4 - aci: analog comparator interrupt flag this bit is set (one) when a comparator output event trig- gers the interrupt mode defined by aci1 and aci0. the analog comparator interrupt routine is executed if the acie bit is set (one) and the i-bit in sreg is set (one). aci is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 - acie: analog comparator interrupt enable when the acie bit is set (one) and the i-bit in the status register is set (one), the analog comparator interrupt is activated. when cleared (zero), the interrupt is disabled. ? bit 2 - acic: analog comparator input capture enable when set (one), this bit enables the input capture function in timer/counter1 to be triggered by the analog compara- tor. the comparator output is in this case directly con- nected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select fea- tures of the timer/counter1 input capture interrupt. when cleared (zero), no connection between the analog compar- ator and the input capture function is given. to make the comparator trigger the timer/counter1 input capture inter- rupt, the ticie1 bit in the timer interrupt mask register (timsk) must be set (one). bit 76543210 $08 ($28) acd - aco aci acie acic acis1 acis0 acsr read/write r/w r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 at90s8515 43 ? bits 1,0 - acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger the analog comparator interrupt. the different settings are shown in table 17. note: when changing the acis1/acis0 bits, the analog com- parator interrupt must be disabled by clearing its inter- rupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. i/o-ports port a port a is an 8-bit bi-directional i/o port. three data memory address locations are allocated for the port a, one each for the data register - porta, $1b($3b), data direction register - ddra, $1a($3a) and the port a input pins - pina, $19($39). the port a input pins address is read only, while the data register and the data direction register are read/write. all port pins have individually selectable pull-up resistors. the port a output buffers can sink 20ma and thus drive led displays directly. when pins pa0 to pa7 are used as inputs and are externally pulled low, they will source cur- rent if the internal pull-up resistors are activated. the port a pins have alternate functions related to the optional external data sram. port a can be configured to be the multiplexed low-order address/data bus during accesses to the external data memory. in this mode, port a has internal pull-up resistors. when port a is set to the alternate function by the sre - external sram enable - bit in the mcucr - mcu control register, the alternate settings override the data direction register. the port a data register - porta the port a data direction register - ddra the port a input pins address - pina the port a input pins address - pina - is not a register, and this address enables access to the physical value on each port a pin. when reading porta the porta data latch is read, and when reading pina, the logical values present on the pins are read. port a as general digital i/o all 8 bits in port a are equal when used as digital i/o pins. pan, general i/o pin: the ddan bit in the ddra register selects the direction of this pin, if ddan is set (one), pan is configured as an output pin. if ddan is cleared (zero), pan is configured as an input pin. if portan is set (one) when the pin configured as an input pin, the mos pull up resistor is activated. to switch the pull up resistor off, the portan has to be cleared (zero) or the pin has to be configured as an output pin. table 17. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle 01reserved 10 comparator interrupt on falling output edge 11 comparator interrupt on rising output edge bit 76543210 $1b ($3b) porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $1a ($3a) dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $19 ($39) pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 pina read/write rrrrrrrr initial value hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z at90s8515 44 n: 7,60, pin number. port a schematics note that all port pins are synchronized. the synchronization latch is however, not shown in the figure. figure 45. porta schematic diagrams (pins pa0 - pa7) port b port b is an 8-bit bi-directional i/o port. three data memory address locations are allocated for the port b, one each for the data register - portb, $18($38), data direction register - ddrb, $17($37) and the port b input pins - pinb, $16($36). the port b input pins address is read only, while the data register and the data direction register are read/write. all port pins have individually selectable pull-up resistors. the port b output buffers can sink 20ma and thus drive led displays directly. when pins pb0 to pb7 are used as inputs and are externally pulled low, they will source cur- rent if the internal pull-up resistors are activated. the port b pins with alternate functions are shown in the following table: table 18. ddan effects on port a pins ddan portan i/o pull up comment 0 0 input no tri-state (hi-z) 0 1 input yes pan will source current if ext. pulled low. 1 0 output no push-pull zero output 1 1 output no push-pull one output at90s8515 45 when the pins are used for the alternate function the ddrb and portb register has to be set according to the alternate function description. the port b data register - portb the port b data direction register - ddrb the port b input pins address - pinb the port b input pins address - pinb - is not a register, and this address enables access to the physical value on each port b pin. when reading portb, the portb data latch is read, and when reading pinb, the logical values present on the pins are read. portb as general digital i/o all 8 bits in port b are equal when used as digital i/o pins. pbn, general i/o pin: the ddbn bit in the ddrb register selects the direction of this pin, if ddbn is set (one), pbn is configured as an output pin. if ddbn is cleared (zero), pbn is configured as an input pin. if portbn is set (one) when the pin configured as an input pin, the mos pull up resistor is activated. to switch the pull up resistor off, the portbn has to be cleared (zero) or the pin has to be configured as an output pin. n: 7,60, pin number. table 19. port b pins alternate functions port pin alternate functions pb0 t0 (timer/counter 0 external counter input) pb1 t1 (timer/counter 1 external counter input) pb2 ain0 (analog comparator positive input) pb3 ain1 (analog comparator negative input) pb4 ss (spi slave select input) pb5 mosi (spi bus master output/slave input) pb6 miso (spi bus master input/slave output) pb7 sck (spi bus serial clock) bit 76543210 $18 ($38) portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $17 ($37) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $16 ($36) pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/write rrrrrrrr initial value hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z table 20. ddbn effects on port b pins ddbn portbn i/o pull up comment 0 0 input no tri-state (hi-z) 0 1 input yes pbn will source current if ext. pulled low. 1 0 output no push-pull zero output 1 1 output no push-pull one output at90s8515 46 alternate functions of portb the alternate pin configuration is as follows: sck - portb, bit 7 sck: master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb7. when the spi is enabled as a master, the data direction of this pin is controlled by ddb7. when the pin is forced to be an input, the pull-up can still be controlled by the portb7 bit. see the description of the spi port for further detatils. miso - portb, bit 6 miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddb6. when the spi is enabled as a slave, the data direction of this pin is controlled by ddb6. when the pin is forced to be an input, the pull-up can still be controlled by the portb6 bit. see the description of the spi port for further detatils. mosi - portb, bit 5 mosi: spi master data output, slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb5. when the spi is enabled as a master, the data direction of this pin is controlled by ddb5. when the pin is forced to be an input, the pull-up can still be controlled by the portb5 bit. see the description of the spi port for further detatils. ss - portb, bit 4 ss : slave port select input. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb5. as a slave, the spi is activated when this pin is driven low. when the spi is enabled as a master, the data direction of this pin is controlled by ddb5. when the pin is forced to be an input, the pull-up can still be con- trolled by the portb5 bit. see the description of the spi port for further detatils. ain1 - portb, bit 3 ain1, analog comparator negative input. when config- ured as an input (ddb3 is cleared (zero)) and with the internal mos pull up resistor switched off (pb3 is cleared (zero)), this pin also serves as the negative input of the on- chip analog comparator. ain0 - portb, bit 2 ain0, analog comparator positive input. when configured as an input (ddb2 is cleared (zero)) and with the internal mos pull up resistor switched off (pb2 is cleared (zero)), this pin also serves as the positive input of the on-chip ana- log comparator. t1 - portb, bit 1 t1, timer/counter1 counter source. see the timer descrip- tion for further details t0 - portb, bit 0 t0: timer/counter0 counter source. see the timer descrip- tion for further details. port b schematics note that all port pins are synchronized. the synchroniza- tion latches are however, not shown in the figures. at90s8515 47 figure 46. portb schematic diagram (pins pb0 and pb1) figure 47. portb schematic diagram (pins pb2 and pb3) at90s8515 48 figure 48. portb schematic diagram (pin pb4) figure 49. portb schematic diagram (pin pb5) data bus d d q q reset reset c c wd wp rd mos pull- up pb4 spi ss mstr spe wp: wd: rl: rp: rd: mstr: spe: write portb write ddrb read portb latch read portb pin read ddrb spi master enable spi enable ddb4 portb4 rl rp data bus d d q q reset reset c c wd wp rd mos pull- up pb5 r r wp: wd: rl: rp: rd: spe: mstr write portb write ddrb read portb latch read portb pin read ddrb spi enable master select ddb5 portb5 spe mstr spi master out spi slave in rl rp at90s8515 49 figure 50. portb schematic diagram (pin pb6) figure 51. portb schematic diagram (pin pb7) data bus d d q q reset reset c c wd wp rd mos pull- up pb6 r r wp: wd: rl: rp: rd: spe: mstr write portb write ddrb read portb latch read portb pin read ddrb spi enable master select ddb6 portb6 spe mstr spi slave out spi master in rl rp data bus d d q q reset reset c c wd wp rd mos pull- up pb7 r r wp: wd: rl: rp: rd: spe: mstr write portb write ddrb read portb latch read portb pin read ddrb spi enable master select ddb7 portb7 spe mstr spi cllock out spi clock in rl rp at90s8515 50 port c port c is an 8-bit bi-directional i/o port. three data memory address locations are allocated for the port c, one each for the data register - portc, $15($35), data direction register - ddrc, $14($34) and the port c input pins - pinc, $13($33). the port c input pins address is read only, while the data register and the data direction register are read/write. all port pins have individually selectable pull-up resistors. the port c output buffers can sink 20ma and thus drive led displays directly. when pins pc0 to pc7 are used as inputs and are externally pulled low, they will source cur- rent if the internal pull-up resistors are activated. the port c pins have alternate functions related to the optional external data sram. port c can be configured to be the high-order address byte during accesses to exter- nal data memory. when port c is set to the alternate function by the sre - external sram enable - bit in the mcucr - mcu control register, the alternate settings override the data direction register. the port c data register - portc the port c data direction register - ddrc the port c input pins address - pinc the port c input pins address - pinc - is not a register, and this address enables access to the physical value on each port c pin. when reading portc, the portc data latch is read, and when reading pinc, the logical values present on the pins are read. portc as general digital i/o all 8 bits in port c are equal when used as digital i/o pins. pcn, general i/o pin: the ddcn bit in the ddrc register selects the direction of this pin, if ddcn is set (one), pcn is configured as an output pin. if ddcn is cleared (zero), pcn is configured as an input pin. if portcn is set (one) when the pin configured as an input pin, the mos pull up resistor is activated. to switch the pull up resistor off, portcn has to be cleared (zero) or the pin has to be configured as an output pin. n: 70, pin number bit 76543210 $15 ($35) portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 portc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $14 ($34) ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $13 ($33) pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 pinc read/write rrrrrrrr initial value hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z table 21. ddcn effects on port c pins ddcn portcn i/o pull up comment 0 0 input no tri-state (hi-z) 0 1 input yes pcn will source current if ext. pulled low. 1 0 output no push-pull zero output 1 1 output no push-pull one output at90s8515 51 port c schematics note that all port pins are synchronized. the synchronization latch is however, not shown in the figure. figure 52. portc schematic diagram (pins pc0 - pc7) port d port d is an 8 bit bi-directional i/o port with internal pull-up resistors. three data memory address locations are allocated for the port d, one each for the data register - portd, $12($32), data direction register - ddrd, $11($31) and the port d input pins - pind, $10($30). the port d input pins address is read only, while the data register and the data direction register are read/write. the port d output buffers can sink 20 ma. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. some port d pins have alternate functions as shown in the following table: when the pins are used for the alternate function the ddrd and portd register has to be set according to the alternate function description. table 22. port d pins alternate functions port pin alternate function pd0 rdx (uart input line ) pd1 tdx (uart output line) pd2 int0 (external interrupt 0 input) pd3 int1 (external interrupt 1 input) pd5 oc1a (timer/counter1 output comparea match output) pd6 wr (write strobe to external memory) pd7 rd (read strobe to external memory) at90s8515 52 the port d data register - portd the port d data direction register - ddrd the port d input pins address - pind the port d input pins address - pind - is not a register, and this address enables access to the physical value on each port d pin. when reading portd, the portd data latch is read, and when reading pind, the logical values present on the pins are read. portd as general digital i/o pdn, general i/o pin: the dddn bit in the ddrd register selects the direction of this pin. if dddn is set (one), pdn is configured as an output pin. if dddn is cleared (zero), pdn is configured as an input pin. if pdn is set (one) when con- figured as an input pin the mos pull up resistor is activated. to switch the pull up resistor off the pdn has to be cleared (zero) or the pin has to be configured as an output pin. n: 7,60, pin number. alternate functions of portd rd - portd, bit 7 rd is the external data memory read control strobe. wr - portd, bit 6 wr is the external data memory write control strobe. oc1- portd, bit 5 oc1, output compare match output: the pd5 pin can serve as an external output when the timer/counter1 com- pare matches. the pd5 pin has to be configured as an out- put (ddd5 set (one)) to serve this function. see the timer/counter1 description for further details, and how to enable the output. the oc1 pin is also the output pin for the pwm mode timer function. int1 - portd, bit 3 int1, external interrupt source 1: the pd3 pin can serve as an external interrupt source to the mcu. see the inter- rupt description for further details, and how to enable the source. int0 - portd, bit 2 int0, external interrupt source 0: the pd2 pin can serve as an external interrupt source to the mcu. see the inter- rupt description for further details, and how to enable the source. txd - portd, bit 1 transmit data (data output pin for the uart). when the uart transmitter is enabled, this pin is configured as an output regardless of the value of ddrd1. rxd - portd, bit 0 receive data (data input pin for the uart). when the uart receiver is enabled this pin is configured as an out- put regardless of the value of ddrd0. when the uart forces this pin to be an input, a logical one in portd0 vill turn on the internal pull-up. bit 76543210 $12 ($32) portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $11 ($31) ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 $10 ($30) pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 pind read/write rrrrrrrr initial value hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z table 23. dddn bits on port d pins dddn portdn i/o pull up comment 0 0 input no tri-state (hi-z) 0 1 input yes pdn will source current if ext. pulled low. 1 0 output no push-pull zero output 1 1 output no push-pull one output at90s8515 53 portd schematics note that all port pins are synchronized. the synchronization latches are however, not shown in the figures. figure 53. portd schematic diagram (pin pd0) figure 54. portd schematic diagram (pin pd1) data bus d d q q reset reset c c wd wp rd mos pull- up pd0 rxd rxen wp: wd: rl: rp: rd: rxd: rxen: write portd write ddrd read portd latch read portd pin read ddrd uart receive data uart receive enable ddd0 portd0 rl rp data bus d d q q reset reset c c wd wp rd rp rl mos pull- up pd1 r r wp: wd: rl: rp: rd: txd: txen: write portd write ddrd read portd latch read portd pin read ddrd uart transmit data uart transmit enable ddd1 portd1 txen txd at90s8515 54 figure 55. portd schematic diagram (pins pd2 and pd3) figure 56. portd schematic diagram (pin pd4) at90s8515 55 figure 57. portd schematic diagram (pin pd5) figure 58. portd schematic diagram (pin pd6) at90s8515 56 figure 59. portd schematic diagram (pin pd7) memory programming program memory lock bits the at90s8515 mcu provides two lock bits which can be left unprogrammed (1) or can be programmed (0) to obtain the additional features listed in table 24. note: the lock bits can only be erased with the chip erase operation. fuse bits the at90s8515 has two fuse bits, spien and fstrt. ? when spien is programmed (0), serial program downloading is enabled. default value is programmed (0). ? when fstrt is programmed (0), the short start-up time is selected. default value is unprogrammed (1). parts with this bit pre-programmed (0) can be delivered on demand. these bits are not accessible in serial programming mode and are not affected by a chip erase. signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both seria (1) land parallel mode. the three bytes reside in a sep- arate address space, and for the at90s8515 they are: 1. $00: $1e (indicates manufactured by atmel) 2. $01: $93 (indicates 8kb flash memory) 3. $02: $01 (indicates 90s8515 device when $01 is $93) note: 1. when both lock bits are programmed (lock mode 3), the signature bytes can not be read in serial mode programming the flash and eeprom atmels at90s8515 offers 8k bytes of in-system repro- grammable flash program memory and 512 bytes of eeprom data memory. the at90s8515 is normally shipped with the on-chip flash program and eeprom data memory arrays in the erased state (i.e. contents = $ff) and ready to be programmed. this device supports a high-voltage (12v) parallel pro- gramming mode and a low-voltage serial programming table 24. lock bit protection modes program lock bits protection type mode lb1 lb2 1 1 1 no program lock features 201 further programming of the flash and eeprom is disabled 300 same as mode 2, but verify is also disabled. at90s8515 57 mode. the +12v is used for programming enable only, and no current of significance is drawn by this pin. the serial programming mode provides a convenient way to down- load the program and data into the at90s8515 inside the users system. the program and data memory arrays on the at90s8515 are programmed byte-by-byte in either programming modes. for the eeprom, an auto-erase cycle is provided with the self-timed programming operation in the serial pro- gramming mode. parallel programming this section describes how to parallel program and verify flash program memory, eeprom data memory + pro- gram memory lock bits and fuse bits in the at90s8515. figure 60. parallel programming signal names in this section, some pins of the at908515 are referenced by signal names describing their functionality during paral- lel programming rather than their pin names. pins not described in the following table are referenced by pin names. the xa1/xa0 bits determine the action taken when the xtal1 pin is given a positive pulse. the bit settings are shown in the following table: when pulsing wr or oe , the command loaded determines the action on input or output. the command is a byte where the different bits are assigned functions as shown in the fol- lowing table: enter programming mode the following algorithm puts the device in parallel program- ming mode: 1. apply 4.5 - 5.5 v between v cc and gnd. 2. set reset and bs pins to 0 and wait at least 100 ns. 3. apply 11.5 - 12.5v to reset . any activity on bs within 100 ns after +12v has been applied to reset will cause the device to fail entering pro- gramming mode. table 25. pin name mapping signal name in programming mode pin name i/o function rdy / bsy pd1 o 0: device is busy programming, 1: device is ready for new command oe pd2 i output enable (active low) wr pd3 i write pulse (active low) bs pd4 i byte select xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 table 26. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 00 load flash or eeprom address (high or low address byte for flash determined by bs) 01 load data (high or low data byte for flash determined by bs) 1 0 load command 1 1 no action, idle table 27. command byte bit coding bit# meaning when set 7 chip erase 6 write fuse bits. located in the data byte at the following bit positions: d5Cspien fuse, d0Cfstrt fuse (note: write 0 to program, 1 to erase) 5 write lock bits. located in the data byte at the following bit positions: d1Clb1, d0: lb2 (note: write 0 to program) 4 write flash or eeprom (determined by bit 0) 3 read signature row 2 read lock and fuse bits. located in the data byte at the following bits positions: d7Clb1, d6Clb2, d5Cspien fuse, d0: fstrt fuse (note: 0 means programmed) 1 read from flash or eeprom (determined by bit 0) 0 0: flash access, 1: eeprom access at90s8515 58 chip erase the chip erase will erase the flash and eeprom memo- ries plus lock bits. the lock bits are not reset until the pro- gram memory has been completely erased. the fuse bits are not changed. a chip erase must be performed before the flash is programmed. load command chip erase 1. set xa1, xa0 to 10. this enables command load- ing. 2. set bs to 0. 3. set pb(7:0) to 1000 0000. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the com- mand, and starts the erase of the flash and eeprom arrays. after pulsing xtal1, give wr a negative pulse to enable lock bit erase at the end of the erase cycle, then wait for at least 10 ms. chip erase does not generate any activity on the rdy/bsy pin. programming the flash load command program flash 1. set xa1, xa0 to 10. this enables command load- ing. 2. set bs to 0 3. set pb(7:0) to 0001 0000. this is the command for flash programming. 4. give xtal1 a positive pulse. this loads the com- mand. load address low byte 1. set xa1, xa0 to 00. this enables address loading. 2. set bs to 0. this selects low address. 3. set pb(7:0) = address low byte ($00 - $ff) 4. give xtal1 a positive pulse. this loads the address low byte. load address high byte 1. set xa1, xa0 to 00. this enables address loading. 2. set bs to 1. this selects high address. 3. set pb(7:0) = address high byte ($00 - $0f) 4. give xtal1 a positive pulse. this loads the address high byte. load data byte 1. set xa1, xa0 to 01. this enables data loading. 2. set pb(7:0) = data low byte ($00 - $ff) 3. give xtal1 a positive pulse. this loads the data byte. write data low byte 1. set bs to (0). 2. give wr a negative pulse. this starts programming of the data byte. rdy/bsy goes low. 3. wait until rdy/bsy goes high to program the next byte. load data byte 1. set xa1, xa0 to 01. this enables data loading. 2. set pb(7:0) = data high byte ($00 - $ff) 3. give xtal1 a positive pulse. this loads the data byte. write data high byte 1. set bs to 1. 2. give wr a negative pulse. this starts programming of the data byte. rdy / bsy goes low. 3. wait until rdy / bsy goes high to program the next byte. the loaded command and address are retained in the device during programming. to simplify programming, the following should be considered. ? the command for flash programming needs only be loaded before programming of the first byte. ? address high byte needs only be loaded before programming a new 256 word page in the flash. at90s8515 59 figure 61. programming flash low byte figure 62. programming flash high byte $10 addr. low addr. high data low pb0 - pb7 xa1 xa2 bs xtal 1 wr rdy/bsy reset oe +12v data high pb0 - pb7 xa1 xa0 bs xtal1 wr rdy/bsy reset +12v oe at90s8515 60 programming the eeprom the programming algorithm for the eeprom data memory is as follows (refer to flash programming for details on command, address and data loading): 1. load command 0001 0001. 2. load low eeprom address ($00 - $ff) 3. load high eeprom address ($00 - $01) 4. load low eeprom data ($00 - $ff) 5. give wr a negative pulse and wait for rdy/bsy to go high. the command needs only be loaded before programming the first byte. reading the flash the algorithm for reading the flash memory is as follows (refer to flash programming for details on command, address and data loading): 1. load command 0000 0010. 2. load low address ($00 - $ff) 3. load high address ($00 - $0f) 4. set oe to 0, and bs to 0. the low data byte can now be read at pb(7:0) 5. set bs to 1. the high data byte can now be read from pb(7:0) 6. set oe to 1. the command needs only be loaded before reading the first byte. reading the eeprom the algorithm for reading the eeprom memory is as fol- lows (refer to flash programming for details on command, address and data loading): 1. load command 0000 0011. 2. load low eeprom address ($00 - $ff) 3. load high eeprom address ($00 - $01) 4. set oe to 0, and bs to 0. the eeprom data byte can now be read at pb(7:0) 5. set oe to 1. the command needs only be loaded before reading the first byte. programming the fuse bits the algorithm for programming the fuse bits is as follows (refer to flash programming for details on command, address and data loading): 1. load command 0100 0000. 2. load data. bit 5 = 0 programs the spien fuse bit. bit 5 = 1 erases the spien fuse bit. bit 0 = 0 programs the fstrt fuse bit. bit 5 = 1 erases the fstrt fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. programming the lock bits the algorithm for programming the lock bits is as follows (refer to flash programming for details on command, address and data loading): 1. load command 0010 0000. 2. load data. bit 2 = 0 programs lock bit2 bit 1 = 0 programs lock bit1 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing a chip erase. reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as fol- lows (refer to flash programming for details on command, address and data loading): 1. load command 0000 0100. 2. set oe to 0, and bs to 1. the status of fuse and lock bits can now be read at pb(7:0) bit 7: lock bit1 (0 means programmed) bit 6: lock bit2 (0 means programmed) bit 5: spien fuse (0 means programmed, 1 means erased) bit 0: fstrt fuse (0 means programmed, 1 means erased) 3. set oe to 1. observe especially that bs needs to be set to 1. reading the signature bytes the algorithm for reading the signature bytes bits is as fol- lows (refer to flash programming for details on command, address and data loading): 1. load command 0000 1000. 2. load low address ($00 - $02) 3. set oe to 0, and bs to 0. the selected signature byte can now be read at pb(7:0) 4. set oe to 1. the command needs only be programmed before reading the first byte. at90s8515 61 parallel programming characteristics figure 63. parallel programming timing note: 1. if t wpwl is held longer than t wlrh , no rdy/bsy pulse will be seen. data & contol (pb0-7, xa0/1, bs) data write read xtal1 t xhxl t wlwh t dvxh t xlwl t xlol t oldv t xhdx t bvwl t whrl t wlrh wr rdy/bsy oe table 28. parallel programming characteristics t a = 21 c to 27 c, v cc = 4.5 - 5.5v symbol parameter min typ max units t dvxh data and control setup before xtal1 high 67 ns t xhxl xtal1 pulse width high 67 ns t xldh data and control hold after xtal1 high 67 ns t bvwl bs valid to wr low 67 ns t wlwh wr pulse width low 67 ns t whrl wr high to rdy/bsy low (1) 20 ns t xlol xtal1 low to oe low 67 ns t oldv oe low to data valid 20 ns t wlrh wr low to rdy/bsy high (1) 0.5 0.7 0.9 ms at90s8515 62 serial downloading both the program and data memory arrays can be pro- grammed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (output). after reset is set low, the pro- gramming enable instruction needs to be executed first before program/erase operations can be executed. when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into $ff. the program and eeprom memory arrays have separate address spaces: $0000 to $0fff for program memory and $0000 to $01ff for eeprom memory. either an external system clock is supplied at pin xtal1 or a crystal needs to be connected across pins xtal1 and xtal2.the minimum low and high periods for the serial clock (sck) input are defined as follows: low:> 2 xtal1 clock cycle high:> 2 xtal1 clock cycles data polling when a new byte has been written and is being pro- grammed into the flash or eeprom, reading the address location being programmed will give the value $7f. at the time the device is ready for a new byte, the programmed value will read correctly. this is used to determine when the next byte can be written. this will not work for the value $7f, so when programming this value, the user will have to wait for at least 4 ms before programming the next byte. as a chip-erased device contains $ff in all locations, pro- gramming of addresses that are meant to contain $ff, can be skipped. this does not apply if the eeprom is re-pro- grammed without chip-erasing the device. in this case, data polling cannot be used for the values $7f and $ff, and the user will have to wait at least 4ms before program- ming the next byte. serial programming algorithm to program and verify the at90s8515 in the serial pro- gramming mode, the following sequence is recommended (see four byte instruction formats in table 29 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to 0. if a crystal is not connected across pins xtal1 and xtal2, apply a clock signal to the xtal1 pin. in some systems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two xtal1 cycles duration after sck has been set to 0. 2. wait for at least 20 ms and enable serial program- ming by sending the programming enable serial instruction to pin mosi/pb5. 3. when issuing the third byte in programming enable, the value sent as byte number two ($53), will echo back during transmission of byte number three. in any case, all four bytes in programming enable must be transmitted. if the $53 did not echo back, give sck a positive pulse and issue a new programming enable command. if the $53 is not seen within 32 attempts, there is no functional device connected. 4. if a chip erase is performed (must be done to erase the flash), wait 10 ms, give reset a positive pulse, and start over from step 2. 5. the flash or eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. an eeprom memory location is first automatically erased before new data is written. use data polling to detect when the next byte in the flash or eeprom can be written. in a chip erased device, no $ffs in the data file(s) need to be programmed. when programming locations with $7f, wait 4 ms before writing the next byte. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output miso/pb6. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set xtal1 to 0 (if a crystal is not used). set reset to 1. tu r n v cc power off at90s8515 63 note: a = address high bits b = address low bits h = 0 - low byte, 1 - high byte o = data out i = data in x = dont care 1 = lock bit 1 2 = lock bit 2 figure 64. serial programming and verify when writing serial data to the at90s8515, data is clocked on the rising edge of clk. when reading data from the at90s8515, data is clocked on the falling edge of clk. see figure 65 for an explana- tion. table 29. serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming after reset goes low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase both 8k & 512byte memory arrays read program memory 0010 h 000 xxxx aaaa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a:b write program memory 0100 h 000 xxxx aaaa bbbb bbbb iiii iiii write h(high or low) data i to program memory at word address a:b read eeprom memory 1010 0000 xxxx xxx 0 bbbb bbbb oooo oooo read data o from eeprom memory at address a:b write eeprom memory 1100 0000 xxxx xxx 0 bbbb bbbb iiii iiii write data i to eeprom memory at address a:b write lock bits 1010 1100 111x x 21 x xxxx xxxx xxxx xxxx write lock bits. set bits 1,2 =0 to program lock bits. read device code 0011 0000 xxxx xxxx xxxx xx bb oooo oooo read device code o at address b at90s8515 64 figure 65. serial programming waveforms serial programming characteristics figure 66. serial programming timing absolute maximum ratings* mosi miso sck t ovsh t shsl t slsh t shox t sliv table 30. serial programming characteristics t a = -40 c to 85 c, v cc = 2.7 - 6.0v (unless otherwise noted) symbol parameter min typ max units 1/t clcl oscillator frequency (v cc = 2.7 - 4.0v) 0 4 mhz t clcl oscillator period (v cc = 2.7 - 4.0v) 250 ns 1/t clcl oscillator frequency (v cc = 4.0 - 6.0v) 0 8 mhz t clcl oscillator period (v cc = 4.0 - 6.0v) 125 ns t shsl sck pulse width high 2 t clcl ns t slsh sck pulse width low 2 t clcl ns t ovsh mosi setup to sck high t clcl ns t shox mosi hold after sck high 2 t clcl ns t sliv sck low to miso valid 10 16 32 ns operating temperature ................................. -40 c to +105 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .................................... -65 c to +150 c voltage on any pin except reset with respect to ground ......................................-1.0v to +7.0v maximum operating voltage ............................................ 6.6v i/o pin maximum current ........................................... 40.0 ma maximum current v cc and gnd .............................. 140.0 ma at90s8515 65 notes: 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10 ma maximum total i ol for all output pins: 80 ma port a: 26 ma ports a, b, d: 15 ma maximum total i ol for all output pins: 70 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. minimum v cc for power down is 2v. dc characteristics t a = -40 c to 85 c, v cc = 2.7v to 6.0v (unless otherwise noted) symbol parameter condition min typ max units v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage (except xtal1, reset) 0.2 v cc + 0.9 v cc + 0.5 v v ih1 input high voltage (xtal1, reset) 0.7 v cc v cc + 0.5 v v ol output low voltage (1) (ports b,c,d) i ol = 20 ma, v cc = 5v i ol = 10 ma, v cc = 2.7v 0.5 v v oh output high voltage (ports b,c,d) i hi = 10 ma, v cc = 5v i hi = 5 ma, v cc = 2.7v 4.5 v i oh output source current (ports b,c,d) v cc = 5v v cc = 2.7v 10 5 ma i ol output sink current (port b,c,d) v cc = 5v v cc = 2.7v 20 10 ma rrst reset pulldown resistor 10 50 k w r i/o i/o pin pull-up resistor 35 120 k w i cc power supply current active mode, 3v, 4mhz 3.5 ma idle mode 3v, 4mhz 1000 m a i cc power down mode (2) wdt enabled, 3v 50 m a wdt disabled, 3v <1 m a v acio analog comparator input offset voltage v cc = 5v 20 mv i aclk analog comparator input leakage current 1510na t acpd analog comparator propagation delay v cc = 2.7v v cc = 4.0v 750 500 ns at90s8515 66 external clock drive waveforms figure 67. external ram timing t3 is only present when wait-state is enabled. external clock drive symbol parameter v cc = 2.7v to 6.0v v cc = 4.0v to 6.0v units min max min max 1/t clcl oscillator frequency 0 4 0 8 mhz t clcl clock period 250 125 ns t chcx high time 0 0 ns t clcx low time 0 0 ns t clch rise time 1.6 0.5 m s t chcl fall time 1.6 0.5 m s system clock o ale wr rd data / address [7..0] data / address [7..0] address [15..8] address address address t1 t2 t3 t4 prev. address prev. address prev. address 1 0 4 213 3a 5 10 12 14 15 11 8 9 16 7 6 3b data data write read addr. addr. at90s8515 67 external data memory timing table 31. external data memory characteristics, 4.0 - 6.0 volts, no wait state symbol parameter 8 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 8.0 mhz 1t lhll ale pulse width 32.5 0.5t clcl -30.0 ns 2t avll address valid a to ale low 22.5 0.5t clcl -40.0 ns 3a t llax_st address hold after ale low, st/std/sts instructions 67.5 0.5t clcl +5.0 ns 3b t llax_ld address hold after ale low, ld/ldd/lds instructions 15.0 15.0 ns 4t avllc address valid c to ale low 22.5 0.5t clcl -40.0 ns 5t avrl address valid to rd low 95.0 1.0t clcl -30.0 ns 6t avwl address valid to wr low 157.5 1.5t clcl -30.0 ns 7t llwl ale low to wr low 105.0 145 1.0t clcl -20.0 1.0t clcl +20.0 ns 8t llrl ale low to rd low 42.5 82.5 0.5t clcl -20.0 0.5t clcl +20.0 ns 9t dvrh data setup to rd high 60.0 60.0 ns 10 t rldv read low to data valid 70.0 1.0t clcl -55.0 ns 11 t rhdx data hold after rd high 0.0 0.0 ns 12 t rlrh rd pulse width 105.0 1.0t clcl -20.0 ns 13 t dvwl data setup to wr low 27.5 0.5t clcl -35.0 ns 14 t whdx data hold after wr high 0.0 0.0 ns 15 t dvwh data valid to wr high 95.0 1.0t clcl -30.0 ns 16 t wlwh wr pulse width 42.5 0.5t clcl -20.0 ns table 32. external data memory characterizatics, 4.0 - 6.0 volts, 1 cycle wait state symbol parameter 8 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 8.0 mhz 10 t rldv read low to data valid 195.0 2.0t clcl -55.0 ns 12 t rlrh rd pulse width 230.0 2.0t clcl -20.0 ns 15 t dvwh data valid to wr high 220.0 2.0t clcl -30.0 ns 16 t wlwh wr pulse width 167.5 1.5t clcl -20.0 ns at90s8515 68 table 33. external data memory characteristics, 2.7 - 6.0 volts, no wait state symbol parameter 8 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 4.0 mhz 1t lhll ale pulse width 70.0 0.5t clcl -55.0 ns 2t avll address valid a to ale low 60.0 0.5t clcl -65.0 ns 3a t llax_st address hold after ale low, st/std/sts instructions 130.0 0.5t clcl +5.0 ns 3b t llax_ld address hold after ale low, ld/ldd/lds instructions 15.0 15.0 ns 4t avllc address valid c to ale low 60.0 0.5t clcl -65.0 ns 5t avrl address valid to rd low 200.0 1.0t clcl -50.0 ns 6t avwl address valid to wr low 325.0 1.5t clcl -50.0 ns 7t llwl ale low to wr low 230.0 270.0 1.0t clcl -20.0 1.0t clcl +20.0 ns 8t llrl ale low to rd low 105.0 145.0 0.5t clcl -20.0 0.5t clcl +20.0 ns 9t dvrh data setup to rd high 95.0 95.0 ns 10 t rldv read low to data valid 170.0 1.0t clcl -80.0 ns 11 t rhdx data hold after rd high 0.0 0.0 ns 12 t rlrh rd pulse width 230.0 1.0t clcl -20.0 ns 13 t dvwl data setup to wr low 70.0 0.5t clcl -55.0 ns 14 t whdx data hold after wr high 0.0 0.0 ns 15 t dvwh data valid to wr high 210.0 1.0t clcl -40.0 ns 16 t wlwh wr pulse width 105.0 0.5t clcl -20.0 ns table 34. external data memory characteristics, 2.7 - 6.0 volts, 1 cycle wait state symbol parameter 8 mhz oscillator variable oscillator unit min max min max 01/t clcl oscillator frequency 0.0 8.0 mhz 10 t rldv read low to data valid 420.00 2.0t clcl -80.0 ns 12 t rlrh rd pulse width 480.0 2.0t clcl -20.0 ns 15 t dvwh data valid to wr high 460.0 2.0t clcl -40.0 ns 16 t wlwh wr pulse width 355.0 1.5t clcl -20.0 ns at90s8515 69 0 5 10 15 20 25 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 i (ma) cc frequency (mhz) active supply current vs. frequency t = 25?c a v = 5.5v cc v = 5.0v cc v = 4.5v cc v = 4.0v cc v = 3.6v cc v = 3.3v cc v = 3.0v cc v = 2.7v cc v = 6.0v cc 2 4 6 8 10 12 0 0 1 2 3 4 5 6 7 8 9 101112131415 frequency (mhz) i (ma) cc idle supply current vs. frequency t = 25 ? c a v = 6.0v cc v = 5.5v cc v = 5.0v cc v = 4.5v cc v = 4.0v cc v = 3.6v cc v = 3.3v cc v = 3.0v cc v = 2.7v cc 0 2 4 6 8 10 12 14 2 2.5 3 3.5 4 4.5 5 5.5 6 v (v) cc i (ma) cc active supply current vs. supply voltage frequency = 4 mhz t = -40?c a t = 85?c a 0 0.5 1 1.5 2 2.5 3 3.5 4 23456 v (v) cc i (ma) cc idle supply current vs. supply voltage frequency = 4 mhz t = -40?c a t = 85?c a 2.5 3.5 4.5 5.5 0 2 4 6 8 10 12 2 3456 v (v) cc i (a) cc power down supply current vs. vcc watchdog timer disabled t = 85?c a t = 70?c a t = 45?c a t = 25?c a t = -40?c a 0 20 40 60 80 100 120 140 2 2.5 3 3.5 4 4.5 5 5.5 6 v (v) cc i (a) cc power down supply current vs. vcc watchdog timer enabled t = 25?c a t = 85?c a 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 23456 v (v) cc i (ma) cc analog comparator supply current vs. vcc t = -40?c a t = 85?c a 200 400 600 800 1000 1200 1400 1600 23456 v (v) cc f (khz) rc rc oscillator frequency vs. vcc t = 85 ? c a t = 25 ? c a at90s8515 70 0 2 4 6 8 10 12 14 16 23456 v (v) cc freq (mhz) typical max. operating frequency t = 0?c a t = 25?c a t = 85?c a 0 2 4 6 8 10 12 14 16 18 012345 common mode voltage (v) offset voltage (mv) analog comparator offset voltage vs. common mode voltage v = 5v cc t = 25?c a t = 45?c a t = 70?c a t = 80?c a analog comparator input leakage current v cc = 6v, t a = 25?c v in (v) acil (na) 0 60 50 40 30 20 10 0 -10 0.5 1.5 1 2 2.5 3.5 3 4 4.5 5 6 6.5 7 5.5 0 1 2 3 4 5 6 7 8 9 10 0 0.5 1 1.5 2 2.5 common mode voltage (v) offset voltage (mv) analog comparator offset voltage vs. common mode voltage v = 2.7v cc t = 25?c a t = 45?c a t = 70?c a t = 85?c a at90s8515 71 note: charts show typical values. 0 20 40 60 80 100 120 012345 v (v) in i (ua) op pull-up resistor current vs. input voltage v = 5v cc t = 25?c a t = 85?c a 0 2 4 6 8 10 12 14 16 18 20 012345 v (v) oh i (ma) oh i/o pin source current vs. output voltage v = 5v cc t = 25?c a t = 85?c a 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 v (v) ol i (ma) ol i/o pin sink current vs. output voltage v = 5v cc t = 25?c a t = 85?c a 0 0.5 1 1.5 2 2.5 2.7v 4.0v 5.0v v cc threshold voltage (v) i/o pin input threshold vs. vcc 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 v (v) in i (ua) op pull-up resistor current vs. input voltage v = 2.7v cc t = 25?c a t = 85?c a 0 1 2 3 4 5 6 0 0.5 1 1.5 2 2.5 v (v) oh i (ma) oh i/o pin source current vs. output voltage v = 2.7v cc t = 25?c a t = 85?c a 0 5 10 15 20 25 0 0.5 1 1.5 2 v (v) ol i (ma) ol i/o pin sink current vs. output voltage v = 2.7v cc t = 25?c a t = 85?c a 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 2.7v 4.0v 5.0v v cc input hysteresis (v) i/o pin input hysteresis vs. vcc at90s8515 72 at90s8515 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page $3f ($5f) sreg i t h s v n z c 18 $3e ($5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 19 $3d ($5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 19 $3c ($5c) reserved $3b ($5b) gimsk int1 int0 - - - - - -24 $3a ($5a) gifr intf1 intf0 24 $39 ($59) timsk toie1 ocie1a ocie1b - ticie1 - toie0 -24 $38 ($58) tifr tov1 ocf1a ocf1b -icf1 -tov0 -25 $37 ($57) reserved $36 ($56) reserved $35 ($55) mcucr sre srw se sm isc11 isc10 isc01 isc00 26 $34 ($54) reserved $33 ($53) tccr0 - - - - - cs02 cs01 cs00 29 $32 ($52) tcnt0 timer/counter0 (8 bit) 30 $31 ($51) reserved $30 ($50) reserved $2f ($4f) tccr1a com1a1 com1a0 com1b1 com1b0 - -pwm11pwm10 32 $2e ($4e) tccr1b icnc1 ices1 - - ctc1 cs12 cs11 cs10 33 $2d ($4d) tcnt1h timer/counter1 - counter register high byte 34 $2c ($4c) tcnt1l timer/counter1 - counter register low byte 34 $2b ($4b) ocr1ah timer/counter1 - output compare register a high byte 35 $2a ($4a) ocr1al timer/counter1 - output compare register a low byte 35 $29 ($49) ocr1bh timer/counter1 - output compare register b high byte 35 $28 ($48) ocr1bl timer/counter1 - output compare register b low byte 35 $27 ($47) reserved $26 ($46) reserved $25 ($45) icr1h timer/counter1 - input capture register high byte 36 $24 ($44) icr1l timer/counter1 - input capture register low byte 36 $23 ($43) reserved $22 ($42) reserved $21 ($41) wdtcr - - - wdtoe wde wdp2 wdp1 wdp0 38 $20 ($40) reserved $1f ($3f) reserved - - - - - - - eear8 39 $1e ($3e) eearl eeprom address register low byte 39 $1d ($3d) eedr eeprom data register 39 $1c ($3c) eecr - - - - - eemwe eewe eere 40 $1b ($3b) porta porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 54 $1a ($3a) ddra dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 54 $19 ($39) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 54 $18 ($38) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 56 $17 ($37) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 56 $16 ($36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 56 $15 ($35) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 61 $14 ($34) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 61 $13 ($33) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 61 $12 ($32) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 63 $11 ($31) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 63 $10 ($30) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 63 $0f ($2f) spdr spi data register 45 $0e ($2e) spsr spif wcol - - - - - -44 $0d ($2d) spcr spie spe dord mstr cpol cpha spr1 spr0 44 $0c ($2c) udr uart i/o data register 48 $0b ($2b) usr rxc txc udre fe or - - -48 $0a ($2a) ucr rxcie txcie udrie rxen txen chr9 rxb8 txb8 49 $09 ($29) ubrr uart baud rate register 51 $08 ($28) acsr acd - aco aci acie acic acis1 acis0 52 reserved $00 ($20) reserved at90s8515 73 at90s8515 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd ? rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd ? rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl ? rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd ? rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd ? rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd ? rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd ? rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl ? rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd ? rd rr z,n,v 1 andi rd, k logical and register and constant rd ? rd k z,n,v 1 or rd, rr logical or registers rd ? rd v rr z,n,v 1 ori rd, k logical or register and constant rd ? rd v k z,n,v 1 eor rd, rr exclusive or registers rd ? rd ? rr z,n,v 1 com rd ones complement rd ? $ff - rd z,c,n,v 1 neg rd twos complement rd ? $00 - rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd ? rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd ? rd ($ff - k) z,n,v 1 inc rd increment rd ? rd + 1 z,n,v 1 dec rd decrement rd ? rd - 1 z,n,v 1 tst rd test for zero or minus rd ? rd rd z,n,v 1 clr rd clear register rd ? rd ? rd z,n,v 1 ser rd set register rd ? $ff none 1 branch instructions rjmp k relative jump pc ? pc + k + 1 none 2 ijmp indirect jump to (z) pc ? z none 2 rcall k relative subroutine call pc ? pc + k + 1 none 3 icall indirect call to (z) pc ? znone3 ret subroutine return pc ? stack none 4 reti interrupt return pc ? stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc ? pc + 2 or 3 none 1 / 2 cp rd,rr compare rd - rr z, n,v,c,h 1 cpc rd,rr compare with carry rd - rr - c z, n,v,c,h 1 cpi rd,k compare register with immediate rd - k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc ? pc + 2 or 3 none 1 / 2 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc ? pc + 2 or 3 none 1 / 2 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc ? pc + 2 or 3 none 1 / 2 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc ? pc + 2 or 3 none 1 / 2 brbs s, k branch if status flag set if (sreg(s) = 1) then pc ? pc+k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc ? pc+k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc ? pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc ? pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc ? pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc ? pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc ? pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc ? pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc ? pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc ? pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n ? v= 0) then pc ? pc + k + 1 none 1 / 2 brlt k branch if less than zero, signed if (n ? v= 1) then pc ? pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc ? pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc ? pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc ? pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc ? pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc ? pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc ? pc + k + 1 none 1 / 2 brie k branch if interrupt enabled if ( i = 1) then pc ? pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if ( i = 0) then pc ? pc + k + 1 none 1 / 2 at90s8515 74 at90s8515 instruction set summary mnemonics operands description operation flags #clocks data transfer instructions mov rd, rr move between registers rd ? rr none 1 ldi rd, k load immediate rd ? knone1 ld rd, x load indirect rd ? (x) none 2 ld rd, x+ load indirect and post-inc. rd ? (x), x ? x + 1 none 2 ld rd, - x load indirect and pre-dec. x ? x - 1, rd ? (x) none 2 ld rd, y load indirect rd ? (y) none 2 ld rd, y+ load indirect and post-inc. rd ? (y), y ? y + 1 none 2 ld rd, - y load indirect and pre-dec. y ? y - 1, rd ? (y) none 2 ldd rd,y+q load indirect with displacement rd ? (y + q) none 2 ld rd, z load indirect rd ? (z) none 2 ld rd, z+ load indirect and post-inc. rd ? (z), z ? z+1 none 2 ld rd, -z load indirect and pre-dec. z ? z - 1, rd ? (z) none 2 ldd rd, z+q load indirect with displacement rd ? (z + q) none 2 lds rd, k load direct from sram rd ? (k) none 2 st x, rr store indirect (x) ? rr none 2 st x+, rr store indirect and post-inc. (x) ? rr, x ? x + 1 none 2 st - x, rr store indirect and pre-dec. x ? x - 1, (x) ? rr none 2 st y, rr store indirect (y) ? rr none 2 st y+, rr store indirect and post-inc. (y) ? rr, y ? y + 1 none 2 st - y, rr store indirect and pre-dec. y ? y - 1, (y) ? rr none 2 std y+q,rr store indirect with displacement (y + q) ? rr none 2 st z, rr store indirect (z) ? rr none 2 st z+, rr store indirect and post-inc. (z) ? rr, z ? z + 1 none 2 st -z, rr store indirect and pre-dec. z ? z - 1, (z) ? rr none 2 std z+q,rr store indirect with displacement (z + q) ? rr none 2 sts k, rr store direct to sram (k) ? rr none 2 lpm load program memory r0 ? (z) none 3 in rd, p in port rd ? pnone1 out p, rr out port p ? rr none 1 push rr push register on stack stack ? rr none 2 pop rd pop register from stack rd ? stack none 2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) ? 1none2 cbi p,b clear bit in i/o register i/o(p,b) ? 0none2 lsl rd logical shift left rd(n+1) ? rd(n), rd(0) ? 0 z,c,n,v 1 lsr rd logical shift right rd(n) ? rd(n+1), rd(7) ? 0 z,c,n,v 1 rol rd rotate left through carry rd(0) ? c,rd(n+1) ? rd(n),c ? rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) ? c,rd(n) ? rd(n+1),c ? rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) ? rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) ? rd(7..4),rd(7..4) ? rd(3..0) none 1 bset s flag set sreg(s) ? 1 sreg(s) 1 bclr s flag clear sreg(s) ? 0 sreg(s) 1 bst rr, b bit store from register to t t ? rr(b) t 1 bld rd, b bit load from t to register rd(b) ? tnone1 sec set carry c ? 1c1 clc clear carry c ? 0 c 1 sen set negative flag n ? 1n1 cln clear negative flag n ? 0 n 1 sez set zero flag z ? 1z1 clz clear zero flag z ? 0 z 1 sei global interrupt enable i ? 1i1 cli global interrupt disable i ? 0 i 1 ses set signed test flag s ? 1s1 cls clear signed test flag s ? 0 s 1 sev set twos complement overflow. v ? 1v1 clv clear twos complement overflow v ? 0 v 1 set set t in sreg t ? 1t1 clt clear t in sreg t ? 0 t 1 seh set half carry flag in sreg h ? 1h1 clh clear half carry flag in sreg h ? 0 h 1 nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 3 wdr watchdog reset (see specific descr. for wdr/timer) none 1 at90s8515 75 ordering information speed (mhz) power supply ordering code* package operation range 4 2.7 - 6.0v at90s8515-4ac at90s8515-4jc at90s8515-4pc 44a 44j 40p6 commercial (0 c to 70 c) at90s8515-4ai at90s8515-4ji at90s8515-4pi 44a 44j 40p6 industrial (-40 c to 85 c) 8 4.0 - 6.0v at90s8515-8ac AT90S8515-8JC at90s8515-8pc 44a 44j 40p6 commercial (0 c to 70 c) at90s8515-8ai at90s8515-8ji at90s8515-8pi 44a 44j 40p6 industrial (-40 c to 85 c) package type 44a 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 44j 44-lead, plastic j-leaded chip carrier (plcc) 40p6 40-lead, 0.600 wide, plastic dual inline package (pdip) at90s8515 76 packaging information *controlling dimension: millimeters .045(1.14) x 45 pin no. 1 identify .045(1.14) x 30 - 45 .012(.305) .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) ref sq .032(.813) .026(.660) .050(1.27) typ .022(.559) x 45 max (3x) .656(16.7) .650(16.5) .695(17.7) .685(17.4) sq sq 2.07(52.6) 2.04(51.8) pin 1 .566(14.4) .530(13.5) .090(2.29) max .005(.127) min .065(1.65) .015(.381) .022(.559) .014(.356) .065(1.65) .041(1.04) 0 15 ref .690(17.5) .610(15.5) .630(16.0) .590(15.0) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) seating plane .220(5.59) max 1.900(48.26) ref 44a, 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) dimensions in millimeters and (inches)* 44j, 44-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) 40p6, 40-lead, 0.600" wide, plastic dual inline package (pdip) dimensions in inches and (millimeters) jedec standard ms-011 ac |
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